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Message-ID: <175495482437.157244.12960551735480282394.b4-ty@kernel.org>
Date: Mon, 11 Aug 2025 18:26:54 -0500
From: Bjorn Andersson <andersson@...nel.org>
To: Konrad Dybcio <konradybcio@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	George Moussalem <george.moussalem@...look.com>
Cc: linux-arm-msm@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Konrad Dybcio <konrad.dybcio@....qualcomm.com>
Subject: Re: [PATCH v5 0/2] Add CMN PLL clock controller support for IPQ5018


On Mon, 21 Jul 2025 10:04:34 +0400, George Moussalem wrote:
> The CMN PLL block of IPQ5018 supplies output clocks for XO at 24 MHZ,
> sleep at 32KHZ, and the ethernet block at 50MHZ.
> 
> This patch series extends the CMN PLL driver to support IPQ5018. It also
> adds the SoC specific header file to export the CMN PLL output clock
> specifiers for IPQ5018. A new table of output clocks is added for the
> CMN PLL of IPQ5018, which is acquired from the device according to the
> compatible.
> 
> [...]

Applied, thanks!

[1/2] arm64: dts: ipq5018: Add CMN PLL node
      commit: c006b249c54441dd8a3a493c7c87158f441f8178
[2/2] arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
      commit: 5ca3d42384a66bcb66f91d75da16ec9e9f053aab

Best regards,
-- 
Bjorn Andersson <andersson@...nel.org>

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