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Message-ID: <CAMuHMdX_w6aOAnTqZg+=OqKAk_xVPLHFZU9+VAVsh04y186ArA@mail.gmail.com>
Date: Mon, 11 Aug 2025 09:46:08 +0200
From: Geert Uytterhoeven <geert@...ux-m68k.org>
To: "Lad, Prabhakar" <prabhakar.csengg@...il.com>
Cc: Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh@...nel.org>, 
	Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Magnus Damm <magnus.damm@...il.com>, Bartosz Golaszewski <brgl@...ev.pl>, linux-renesas-soc@...r.kernel.org, 
	linux-gpio@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-kernel@...r.kernel.org, Biju Das <biju.das.jz@...renesas.com>, 
	Fabrizio Castro <fabrizio.castro.jz@...esas.com>, 
	Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>, 
	Thierry Bultel <thierry.bultel.yh@...renesas.com>
Subject: Re: [PATCH v4 1/3] dt-bindings: pinctrl: renesas: document RZ/T2H and
 RZ/N2H SoCs

Hi Prabhakar,

On Fri, 8 Aug 2025 at 23:13, Lad, Prabhakar <prabhakar.csengg@...il.com> wrote:
> On Fri, Aug 8, 2025 at 8:51 PM Geert Uytterhoeven <geert@...ux-m68k.org> wrote:
> > On Fri, 1 Aug 2025 at 17:46, Prabhakar <prabhakar.csengg@...il.com> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > >
> > > Document the pin and GPIO controller IP for the Renesas RZ/T2H
> > > (R9A09G077) and RZ/N2H (R9A09G087) SoCs, and add the shared DTSI
> > > header file used by both the bindings and the driver.
> > >
> > > The RZ/T2H SoC supports 729 pins, while the RZ/N2H supports 576 pins.
> > > Both share the same controller architecture; separate compatible
> > > strings are added for each SoC to distinguish them.
> > >
> > > Co-developed-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> > > Signed-off-by: Thierry Bultel <thierry.bultel.yh@...renesas.com>
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
> > > ---
> > > v3->v4:
> > > - Used patternProperties for pin configuration nodes
> > > - Expanded example nodes

> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzt2h-pinctrl.yaml

> > > +                pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */
> > > +                         <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */
> > > +            };
> > > +
> > > +            sd0-sd-tmp-pins {
> > > +                pins = "RIIC0_SDA", "RIIC0_SCL";
> > > +                input-enable;
> > > +            };
> >
> > Please drop this subnode? It totally confuses me ;-)
> >
> I did drop this in the v5 series [0].
>
> https://lore.kernel.org/all/20250808133017.2053637-2-prabhakar.mahadev-lad.rj@bp.renesas.com/

My bad; I had reviewed v4, but forgot to send them.
When I discovered my old draft, I just sent it out...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

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