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Message-ID: <aJtrrJZCHJfqsMBy@lizhi-Precision-Tower-5810>
Date: Tue, 12 Aug 2025 12:28:28 -0400
From: Frank Li <Frank.li@....com>
To: guoniu.zhou@....nxp.com
Cc: linux-media@...r.kernel.org, devicetree@...r.kernel.org,
imx@...ts.linux.dev, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, rmfrfs@...il.com,
laurent.pinchart@...asonboard.com, martink@...teo.de,
kernel@...i.sm, mchehab@...nel.org, robh@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org, shawnguo@...nel.org,
s.hauer@...gutronix.de, kernel@...gutronix.de, festevam@...il.com
Subject: Re: [PATCH 2/5] arm64: dts: imx8ulp: Add CSI and ISI Nodes
On Tue, Aug 12, 2025 at 04:19:23PM +0800, guoniu.zhou@....nxp.com wrote:
> From: Guoniu Zhou <guoniu.zhou@....com>
>
> The CSI-2 in the i.MX8ULP is almost identical to the version present
> in the i.MX8QXP/QM and is routed to the ISI. Add both the ISI and CSI
> nodes and mark them as disabled by default since capture is dependent
> on an attached camera.
>
> Signed-off-by: Guoniu Zhou <guoniu.zhou@....com>
> ---
suppose dts is last patch because binding and driver will be pickup by
media maintainer first, then shawn pick up dts part.
Reviewed-by: Frank Li <Frank.Li@....com>
> arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 67 ++++++++++++++++++++++
> 1 file changed, 67 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> index 2562a35286c2..71abc2a3d505 100644
> --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi
> @@ -7,6 +7,7 @@
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/power/imx8ulp-power.h>
> +#include <dt-bindings/reset/imx8ulp-pcc-reset.h>
> #include <dt-bindings/thermal/thermal.h>
>
> #include "imx8ulp-pinfunc.h"
> @@ -840,6 +841,72 @@ spdif: spdif@...b0000 {
> dma-names = "rx", "tx";
> status = "disabled";
> };
> +
> + isi: isi@...c0000 {
> + compatible = "fsl,imx8ulp-isi";
> + reg = <0x2dac0000 0x10000>;
> + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&pcc5 IMX8ULP_CLK_ISI>,
> + <&cgc2 IMX8ULP_CLK_LPAV_AXI_DIV>;
> + clock-names = "axi", "apb";
> + power-domains = <&scmi_devpd IMX8ULP_PD_ISI>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + isi_in: endpoint {
> + remote-endpoint = <&mipi_csi_out>;
> + };
> + };
> + };
> + };
> +
> + mipi_csi: csi@...f0000 {
> + compatible = "fsl,imx8ulp-mipi-csi2";
> + reg = <0x2daf0000 0x10000>,
> + <0x2dad0000 0x10000>;
> + clocks = <&pcc5 IMX8ULP_CLK_CSI>,
> + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
> + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
> + <&pcc5 IMX8ULP_CLK_CSI_REGS>;
> + clock-names = "core", "esc", "ui", "pclk";
> + assigned-clocks = <&pcc5 IMX8ULP_CLK_CSI>,
> + <&pcc5 IMX8ULP_CLK_CSI_CLK_ESC>,
> + <&pcc5 IMX8ULP_CLK_CSI_CLK_UI>,
> + <&pcc5 IMX8ULP_CLK_CSI_REGS>;
> + assigned-clock-parents = <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV1>,
> + <&cgc2 IMX8ULP_CLK_PLL4_PFD1_DIV2>,
> + <&cgc2 IMX8ULP_CLK_PLL4_PFD0_DIV1>;
> + assigned-clock-rates = <200000000>,
> + <80000000>,
> + <100000000>,
> + <79200000>;
> + power-domains = <&scmi_devpd IMX8ULP_PD_MIPI_CSI>;
> + resets = <&pcc5 PCC5_CSI_SWRST>,
> + <&pcc5 PCC5_CSI_REGS_SWRST>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + mipi_csi_out: endpoint {
> + remote-endpoint = <&isi_in>;
> + };
> + };
> + };
> + };
> };
>
> gpiod: gpio@...00000 {
> --
> 2.34.1
>
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