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Message-ID: <20250812181422.68286-1-robh@kernel.org>
Date: Tue, 12 Aug 2025 13:14:20 -0500
From: "Rob Herring (Arm)" <robh@...nel.org>
To: Will Deacon <will@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Khuong Dinh <khuong@...amperecomputing.com>,
Tai Nguyen <ttnguyen@....com>
Cc: linux-arm-kernel@...ts.infradead.org,
linux-perf-users@...r.kernel.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: [PATCH] dt-bindings: perf: Convert apm,xgene-pmu to DT schema
Convert the Applied Micro X-Gene PMU binding to DT schema format. It is
a straightforward conversion.
Signed-off-by: Rob Herring (Arm) <robh@...nel.org>
---
.../bindings/perf/apm,xgene-pmu.yaml | 142 ++++++++++++++++++
.../bindings/perf/apm-xgene-pmu.txt | 112 --------------
2 files changed, 142 insertions(+), 112 deletions(-)
create mode 100644 Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
delete mode 100644 Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
diff --git a/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
new file mode 100644
index 000000000000..01f0373eac7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml
@@ -0,0 +1,142 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: APM X-Gene SoC PMU
+
+maintainers:
+ - Tai Nguyen <ttnguyen@....com>
+
+description: |
+ This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
+ The following PMU devices are supported:
+
+ L3C - L3 cache controller
+ IOB - IO bridge
+ MCB - Memory controller bridge
+ MC - Memory controller
+
+properties:
+ compatible:
+ enum:
+ - apm,xgene-pmu
+ - apm,xgene-pmu-v2
+
+ "#address-cells":
+ const: 2
+
+ "#size-cells":
+ const: 2
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ regmap-csw:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ regmap-mcba:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ regmap-mcbb:
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+required:
+ - compatible
+ - regmap-csw
+ - regmap-mcba
+ - regmap-mcbb
+ - reg
+ - interrupts
+
+additionalProperties:
+ type: object
+ additionalProperties: false
+
+ properties:
+ compatible:
+ enum:
+ - apm,xgene-pmu-l3c
+ - apm,xgene-pmu-iob
+ - apm,xgene-pmu-mcb
+ - apm,xgene-pmu-mc
+
+ reg:
+ maxItems: 1
+
+ enable-bit-index:
+ description:
+ Specifies which bit enables the associated resource in MCB or MC subnodes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 31
+
+examples:
+ - |
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pmu@...10000 {
+ compatible = "apm,xgene-pmu-v2";
+ reg = <0x0 0x78810000 0x0 0x1000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ regmap-csw = <&csw>;
+ regmap-mcba = <&mcba>;
+ regmap-mcbb = <&mcbb>;
+ interrupts = <0x0 0x22 0x4>;
+
+ pmul3c@...10000 {
+ compatible = "apm,xgene-pmu-l3c";
+ reg = <0x0 0x7e610000 0x0 0x1000>;
+ };
+
+ pmuiob@...40000 {
+ compatible = "apm,xgene-pmu-iob";
+ reg = <0x0 0x7e940000 0x0 0x1000>;
+ };
+
+ pmucmcb@...10000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e710000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmcb@...30000 {
+ compatible = "apm,xgene-pmu-mcb";
+ reg = <0x0 0x7e730000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@...10000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e810000 0x0 0x1000>;
+ enable-bit-index = <0>;
+ };
+
+ pmucmc@...50000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e850000 0x0 0x1000>;
+ enable-bit-index = <1>;
+ };
+
+ pmucmc@...90000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e890000 0x0 0x1000>;
+ enable-bit-index = <2>;
+ };
+
+ pmucmc@...d0000 {
+ compatible = "apm,xgene-pmu-mc";
+ reg = <0x0 0x7e8d0000 0x0 0x1000>;
+ enable-bit-index = <3>;
+ };
+ };
+ };
diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
deleted file mode 100644
index afb11cf693c0..000000000000
--- a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-* APM X-Gene SoC PMU bindings
-
-This is APM X-Gene SoC PMU (Performance Monitoring Unit) module.
-The following PMU devices are supported:
-
- L3C - L3 cache controller
- IOB - IO bridge
- MCB - Memory controller bridge
- MC - Memory controller
-
-The following section describes the SoC PMU DT node binding.
-
-Required properties:
-- compatible : Shall be "apm,xgene-pmu" for revision 1 or
- "apm,xgene-pmu-v2" for revision 2.
-- regmap-csw : Regmap of the CPU switch fabric (CSW) resource.
-- regmap-mcba : Regmap of the MCB-A (memory bridge) resource.
-- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource.
-- reg : First resource shall be the CPU bus PMU resource.
-- interrupts : Interrupt-specifier for PMU IRQ.
-
-Required properties for L3C subnode:
-- compatible : Shall be "apm,xgene-pmu-l3c".
-- reg : First resource shall be the L3C PMU resource.
-
-Required properties for IOB subnode:
-- compatible : Shall be "apm,xgene-pmu-iob".
-- reg : First resource shall be the IOB PMU resource.
-
-Required properties for MCB subnode:
-- compatible : Shall be "apm,xgene-pmu-mcb".
-- reg : First resource shall be the MCB PMU resource.
-- enable-bit-index : The bit indicates if the according MCB is enabled.
-
-Required properties for MC subnode:
-- compatible : Shall be "apm,xgene-pmu-mc".
-- reg : First resource shall be the MC PMU resource.
-- enable-bit-index : The bit indicates if the according MC is enabled.
-
-Example:
- csw: csw@...00000 {
- compatible = "apm,xgene-csw", "syscon";
- reg = <0x0 0x7e200000 0x0 0x1000>;
- };
-
- mcba: mcba@...00000 {
- compatible = "apm,xgene-mcb", "syscon";
- reg = <0x0 0x7e700000 0x0 0x1000>;
- };
-
- mcbb: mcbb@...20000 {
- compatible = "apm,xgene-mcb", "syscon";
- reg = <0x0 0x7e720000 0x0 0x1000>;
- };
-
- pmu: pmu@...10000 {
- compatible = "apm,xgene-pmu-v2";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- regmap-csw = <&csw>;
- regmap-mcba = <&mcba>;
- regmap-mcbb = <&mcbb>;
- reg = <0x0 0x78810000 0x0 0x1000>;
- interrupts = <0x0 0x22 0x4>;
-
- pmul3c@...10000 {
- compatible = "apm,xgene-pmu-l3c";
- reg = <0x0 0x7e610000 0x0 0x1000>;
- };
-
- pmuiob@...40000 {
- compatible = "apm,xgene-pmu-iob";
- reg = <0x0 0x7e940000 0x0 0x1000>;
- };
-
- pmucmcb@...10000 {
- compatible = "apm,xgene-pmu-mcb";
- reg = <0x0 0x7e710000 0x0 0x1000>;
- enable-bit-index = <0>;
- };
-
- pmucmcb@...30000 {
- compatible = "apm,xgene-pmu-mcb";
- reg = <0x0 0x7e730000 0x0 0x1000>;
- enable-bit-index = <1>;
- };
-
- pmucmc@...10000 {
- compatible = "apm,xgene-pmu-mc";
- reg = <0x0 0x7e810000 0x0 0x1000>;
- enable-bit-index = <0>;
- };
-
- pmucmc@...50000 {
- compatible = "apm,xgene-pmu-mc";
- reg = <0x0 0x7e850000 0x0 0x1000>;
- enable-bit-index = <1>;
- };
-
- pmucmc@...90000 {
- compatible = "apm,xgene-pmu-mc";
- reg = <0x0 0x7e890000 0x0 0x1000>;
- enable-bit-index = <2>;
- };
-
- pmucmc@...d0000 {
- compatible = "apm,xgene-pmu-mc";
- reg = <0x0 0x7e8d0000 0x0 0x1000>;
- enable-bit-index = <3>;
- };
- };
--
2.47.2
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