| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250811154638.95732-8-shradha.t@samsung.com>
Date: Mon, 11 Aug 2025 21:16:33 +0530
From: Shradha Todi <shradha.t@...sung.com>
To: linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-phy@...ts.infradead.org
Cc: mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
robh@...nel.org, bhelgaas@...gle.com, jingoohan1@...il.com,
krzk+dt@...nel.org, conor+dt@...nel.org, alim.akhtar@...sung.com,
vkoul@...nel.org, kishon@...nel.org, arnd@...db.de,
m.szyprowski@...sung.com, jh80.chung@...sung.com, pankaj.dubey@...sung.com,
Shradha Todi <shradha.t@...sung.com>
Subject: [PATCH v3 07/12] dt-bindings: PCI: Add support for Tesla FSD SoC
Add Tesla FSD SoC support for both RC and EP.
Signed-off-by: Shradha Todi <shradha.t@...sung.com>
---
.../bindings/pci/tesla,fsd-pcie-ep.yaml | 91 +++++++++++++++++++
.../bindings/pci/tesla,fsd-pcie.yaml | 77 ++++++++++++++++
2 files changed, 168 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
create mode 100644 Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
new file mode 100644
index 000000000000..8dfe0720e6ab
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie-ep.yaml
@@ -0,0 +1,91 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie-ep.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC series PCIe Endpoint Controller
+
+maintainers:
+ - Shradha Todi <shradha.t@...sung.com>
+
+description:
+ Tesla FSD SoCs PCIe endpoint controller is based on the Synopsys DesignWare
+ PCIe IP and thus inherits all the common properties defined in
+ snps,dw-pcie-ep.yaml
+
+allOf:
+ - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
+
+properties:
+ compatible:
+ const: tesla,fsd-pcie-ep
+
+ reg:
+ maxItems: 4
+
+ reg-names:
+ items:
+ - const: elbi
+ - const: dbi
+ - const: dbi2
+ - const: addr_space
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aux
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ num-lanes:
+ maximum: 4
+
+ phys:
+ maxItems: 1
+
+ samsung,syscon-pcie:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle for system control registers, used to
+ control signals at system level
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - num-lanes
+ - phys
+ - samsung,syscon-pcie
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ bus {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ pcieep0: pcie-ep@...00000 {
+ compatible = "tesla,fsd-pcie-ep";
+ reg = <0x0 0x168b0000 0x0 0x1000>,
+ <0x0 0x16a00000 0x0 0x2000>,
+ <0x0 0x16a01000 0x0 0x80>,
+ <0x0 0x17000000 0x0 0xff0000>;
+ reg-names = "elbi", "dbi", "dbi2", "addr_space";
+ clocks = <&clock_fsys1 PCIE_LINK0_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK0_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ num-lanes = <4>;
+ phys = <&pciephy1>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x50c>;
+ };
+ };
+...
diff --git a/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
new file mode 100644
index 000000000000..533870ab1d73
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/tesla,fsd-pcie.yaml
@@ -0,0 +1,77 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/pci/tesla,fsd-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tesla FSD SoC series PCIe Host Controller
+
+maintainers:
+ - Shradha Todi <shradha.t@...sung.com>
+
+description:
+ Tesla FSD SoCs PCIe host controller inherits all the common
+ properties defined in samsung,exynos-pcie.yaml
+
+allOf:
+ - $ref: /schemas/pci/samsung,exynos-pcie.yaml#
+
+properties:
+ compatible:
+ const: tesla,fsd-pcie
+
+ clocks:
+ maxItems: 4
+
+ clock-names:
+ items:
+ - const: aux
+ - const: dbi
+ - const: mstr
+ - const: slv
+
+ num-lanes:
+ maximum: 4
+
+ samsung,syscon-pcie:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ description: phandle for system control registers, used to
+ control signals at system level
+
+required:
+ - samsung,syscon-pcie
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/fsd-clk.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pcierc1: pcie@...00000 {
+ compatible = "tesla,fsd-pcie";
+ reg = <0x0 0x16b00000 0x0 0x2000>,
+ <0x0 0x168c0000 0x0 0x1000>,
+ <0x0 0x18000000 0x0 0x1000>;
+ reg-names = "dbi", "elbi", "config";
+ ranges = <0x82000000 0x0 0x18001000 0x0 0x18001000 0x0 0xffefff>;
+ clocks = <&clock_fsys1 PCIE_LINK1_IPCLKPORT_AUX_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_DBI_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_MSTR_ACLK>,
+ <&clock_fsys1 PCIE_LINK1_IPCLKPORT_SLV_ACLK>;
+ clock-names = "aux", "dbi", "mstr", "slv";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ dma-coherent;
+ device_type = "pci";
+ interrupts = <GIC_SPI 117 IRQ_TYPE_EDGE_RISING>;
+ num-lanes = <4>;
+ phys = <&pciephy1>;
+ samsung,syscon-pcie = <&sysreg_fsys1 0x510>;
+ };
+ };
+...
--
2.49.0
Powered by blists - more mailing lists