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Message-ID: <702475b58c83704d753c9fabde9eea3ced20586c.camel@icenowy.me>
Date: Tue, 12 Aug 2025 13:56:47 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Drew Fustini <fustini@...nel.org>, Guo Ren <guoren@...nel.org>, Fu Wei
<wefu@...hat.com>, Michael Turquette <mturquette@...libre.com>, Stephen
Boyd <sboyd@...nel.org>, Michal Wilczynski <m.wilczynski@...sung.com>
Cc: linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/4] clk: thead: th1520-ap: set all AXI clocks to
CLK_IS_CRITICAL
在 2025-08-12星期二的 13:42 +0800，Icenowy Zheng写道：
> The AXI crossbar of TH1520 has no proper timeout handling, which
> means
> gating AXI clocks can easily lead to bus timeout and thus system
> hang.
>
> Set all AXI clock gates to CLK_IS_CRITICAL. All these clock gates are
> ungated by default on system reset.
>
> In addition, convert all current CLK_IGNORE_UNUSED usage to
> CLK_IS_CRITICAL to prevent unwanted clock gating.
>
> Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> ---
> drivers/clk/thead/clk-th1520-ap.c | 42 ++++++++++++++++-------------
> --
> 1 file changed, 22 insertions(+), 20 deletions(-)
>
> diff --git a/drivers/clk/thead/clk-th1520-ap.c
> b/drivers/clk/thead/clk-th1520-ap.c
> index 3e81f3051cd6c..0117e5ea1bf58 100644
> --- a/drivers/clk/thead/clk-th1520-ap.c
> +++ b/drivers/clk/thead/clk-th1520-ap.c
> @@ -589,7 +589,7 @@ static struct ccu_div axi4_cpusys2_aclk = {
> .hw.init = CLK_HW_INIT_PARENTS_HW("axi4-
> cpusys2-aclk",
> gmac_pll_clk_parent,
> &ccu_div_ops,
> - 0),
> + CLK_IS_CRITICAL),
> },
> };
>
> @@ -611,7 +611,7 @@ static struct ccu_div axi_aclk = {
> .hw.init = CLK_HW_INIT_PARENTS_DATA("axi-
> aclk",
> axi_parents,
> &ccu_div_ops,
> - 0),
> +
> CLK_IS_CRITICAL),
> },
> };
>
> @@ -760,7 +760,7 @@ static struct ccu_div apb_pclk = {
> .hw.init = CLK_HW_INIT_PARENTS_DATA("apb-
> pclk",
> apb_parents,
> &ccu_div_ops,
> -
> CLK_IGNORE_UNUSED),
> +
> CLK_IS_CRITICAL),
> },
> };
>
> @@ -791,7 +791,7 @@ static struct ccu_div vi_clk = {
> .hw.init = CLK_HW_INIT_PARENTS_HW("vi",
> video_pll_clk_parent,
> &ccu_div_ops,
> - 0),
> + CLK_IS_CRITICAL),
> },
> };
>
> @@ -816,7 +816,7 @@ static struct ccu_div vo_axi_clk = {
> .hw.init = CLK_HW_INIT_PARENTS_HW("vo-axi",
> video_pll_clk_parent,
> &ccu_div_ops,
> - 0),
> + CLK_IS_CRITICAL),
> },
> };
>
> @@ -841,7 +841,7 @@ static struct ccu_div vp_axi_clk = {
> .hw.init = CLK_HW_INIT_PARENTS_HW("vp-axi",
> video_pll_clk_parent,
> &ccu_div_ops,
> - CLK_IGNORE_UNUSED),
> + CLK_IS_CRITICAL),
> },
> };
>
> @@ -902,23 +902,25 @@ static const struct clk_parent_data
> emmc_sdio_ref_clk_pd[] = {
> static CCU_GATE(CLK_BROM, brom_clk, "brom", ahb2_cpusys_hclk_pd,
> 0x100, BIT(4), 0);
> static CCU_GATE(CLK_BMU, bmu_clk, "bmu", axi4_cpusys2_aclk_pd,
> 0x100, BIT(5), 0);
> static CCU_GATE(CLK_AON2CPU_A2X, aon2cpu_a2x_clk, "aon2cpu-a2x",
> axi4_cpusys2_aclk_pd,
> - 0x134, BIT(8), 0);
> + 0x134, BIT(8), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_X2X_CPUSYS, x2x_cpusys_clk, "x2x-cpusys",
> axi4_cpusys2_aclk_pd,
> - 0x134, BIT(7), 0);
> + 0x134, BIT(7), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_CPU2AON_X2H, cpu2aon_x2h_clk, "cpu2aon-x2h",
> axi_aclk_pd,
> - 0x138, BIT(8), CLK_IGNORE_UNUSED);
> + 0x138, BIT(8), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_CPU2PERI_X2H, cpu2peri_x2h_clk, "cpu2peri-x2h",
> axi4_cpusys2_aclk_pd,
> - 0x140, BIT(9), CLK_IGNORE_UNUSED);
> + 0x140, BIT(9), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_PERISYS_APB1_HCLK, perisys_apb1_hclk, "perisys-
> apb1-hclk", perisys_ahb_hclk_pd,
> - 0x150, BIT(9), CLK_IGNORE_UNUSED);
> + 0x150, BIT(9), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_PERISYS_APB2_HCLK, perisys_apb2_hclk, "perisys-
> apb2-hclk", perisys_ahb_hclk_pd,
> - 0x150, BIT(10), CLK_IGNORE_UNUSED);
> + 0x150, BIT(10), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_PERISYS_APB3_HCLK, perisys_apb3_hclk, "perisys-
> apb3-hclk", perisys_ahb_hclk_pd,
> - 0x150, BIT(11), CLK_IGNORE_UNUSED);
> + 0x150, BIT(11), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_PERISYS_APB4_HCLK, perisys_apb4_hclk, "perisys-
> apb4-hclk", perisys_ahb_hclk_pd,
> 0x150, BIT(12), 0);
> static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd,
> 0x1c8, BIT(5), 0);
> static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd,
> 0x1e0, BIT(13), 0);
> +static CCU_GATE(CLK_NPU_AXI, npu_axi_clk, "npu-axi", axi_aclk_pd,
> 0x1c8, BIT(5), CLK_IS_CRITICAL);
> +static CCU_GATE(CLK_CPU2VP, cpu2vp_clk, "cpu2vp", axi_aclk_pd,
> 0x1e0, BIT(13), CLK_IS_CRITICAL);
Oops... sorry, my rebase operation broke this patch.
Previously this patch was the 4th (in the sequence of being written),
but I rebased it to be the 3rd, and this code being in the same chunk
with perisys-apb4-hclk breaked it.
> static CCU_GATE(CLK_EMMC_SDIO, emmc_sdio_clk, "emmc-sdio",
> emmc_sdio_ref_clk_pd, 0x204, BIT(30), 0);
> static CCU_GATE(CLK_GMAC1, gmac1_clk, "gmac1", gmac_pll_clk_pd,
> 0x204, BIT(26), 0);
> static CCU_GATE(CLK_PADCTRL1, padctrl1_clk, "padctrl1",
> perisys_apb_pclk_pd, 0x204, BIT(24), 0);
> @@ -962,11 +964,11 @@ static CCU_GATE(CLK_SRAM2, sram2_clk, "sram2",
> axi_aclk_pd, 0x20c, BIT(2), 0);
> static CCU_GATE(CLK_SRAM3, sram3_clk, "sram3", axi_aclk_pd, 0x20c,
> BIT(1), 0);
>
> static CCU_GATE(CLK_AXI4_VO_ACLK, axi4_vo_aclk, "axi4-vo-aclk",
> - video_pll_clk_pd, 0x0, BIT(0), 0);
> + video_pll_clk_pd, 0x0, BIT(0), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_GPU_CORE, gpu_core_clk, "gpu-core-clk",
> video_pll_clk_pd,
> 0x0, BIT(3), 0);
> static CCU_GATE(CLK_GPU_CFG_ACLK, gpu_cfg_aclk, "gpu-cfg-aclk",
> - video_pll_clk_pd, 0x0, BIT(4), 0);
> + video_pll_clk_pd, 0x0, BIT(4), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_DPU_PIXELCLK0, dpu0_pixelclk, "dpu0-pixelclk",
> dpu0_clk_pd, 0x0, BIT(5), CLK_SET_RATE_PARENT);
> static CCU_GATE(CLK_DPU_PIXELCLK1, dpu1_pixelclk, "dpu1-pixelclk",
> @@ -998,9 +1000,9 @@ static CCU_GATE(CLK_MIPI_DSI1_REFCLK,
> mipi_dsi1_refclk, "mipi-dsi1-refclk",
> static CCU_GATE(CLK_HDMI_I2S, hdmi_i2s_clk, "hdmi-i2s-clk",
> video_pll_clk_pd,
> 0x0, BIT(19), 0);
> static CCU_GATE(CLK_X2H_DPU1_ACLK, x2h_dpu1_aclk, "x2h-dpu1-aclk",
> - video_pll_clk_pd, 0x0, BIT(20), 0);
> + video_pll_clk_pd, 0x0, BIT(20), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_X2H_DPU_ACLK, x2h_dpu_aclk, "x2h-dpu-aclk",
> - video_pll_clk_pd, 0x0, BIT(21), 0);
> + video_pll_clk_pd, 0x0, BIT(21), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_AXI4_VO_PCLK, axi4_vo_pclk, "axi4-vo-pclk",
> video_pll_clk_pd, 0x0, BIT(22), 0);
> static CCU_GATE(CLK_IOPMP_VOSYS_DPU_PCLK, iopmp_vosys_dpu_pclk,
> @@ -1010,11 +1012,11 @@ static CCU_GATE(CLK_IOPMP_VOSYS_DPU1_PCLK,
> iopmp_vosys_dpu1_pclk,
> static CCU_GATE(CLK_IOPMP_VOSYS_GPU_PCLK, iopmp_vosys_gpu_pclk,
> "iopmp-vosys-gpu-pclk", video_pll_clk_pd, 0x0,
> BIT(25), 0);
> static CCU_GATE(CLK_IOPMP_DPU1_ACLK, iopmp_dpu1_aclk, "iopmp-dpu1-
> aclk",
> - video_pll_clk_pd, 0x0, BIT(27), 0);
> + video_pll_clk_pd, 0x0, BIT(27), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_IOPMP_DPU_ACLK, iopmp_dpu_aclk, "iopmp-dpu-
> aclk",
> - video_pll_clk_pd, 0x0, BIT(28), 0);
> + video_pll_clk_pd, 0x0, BIT(28), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_IOPMP_GPU_ACLK, iopmp_gpu_aclk, "iopmp-gpu-
> aclk",
> - video_pll_clk_pd, 0x0, BIT(29), 0);
> + video_pll_clk_pd, 0x0, BIT(29), CLK_IS_CRITICAL);
> static CCU_GATE(CLK_MIPIDSI0_PIXCLK, mipi_dsi0_pixclk, "mipi-dsi0-
> pixclk",
> video_pll_clk_pd, 0x0, BIT(30), 0);
> static CCU_GATE(CLK_MIPIDSI1_PIXCLK, mipi_dsi1_pixclk, "mipi-dsi1-
> pixclk",
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