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Message-ID: <83205cad-14f5-65a1-1818-677335a1ab91@quicinc.com>
Date: Tue, 12 Aug 2025 13:35:20 +0530
From: Dikshita Agarwal <quic_dikshita@...cinc.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>,
Vikash Garodia
<quic_vgarodia@...cinc.com>,
Abhinav Kumar <abhinav.kumar@...ux.dev>,
"Bryan
O'Donoghue" <bryan.odonoghue@...aro.org>,
Mauro Carvalho Chehab
<mchehab@...nel.org>,
Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski
<krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Philipp Zabel
<p.zabel@...gutronix.de>
CC: <linux-media@...r.kernel.org>, <linux-arm-msm@...r.kernel.org>,
<devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 3/3] media: iris: Add support for SM8750 (VPU v3.5)
On 8/4/2025 7:07 PM, Krzysztof Kozlowski wrote:
> Add support for SM8750 Iris codec with major differences against
> previous generation SM8650:
>
> 1. New clocks and new resets, thus new power up and power down
> sequences,
>
> 2. New WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 register programmed
> during boot-up
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
> ---
> .../platform/qcom/iris/iris_platform_common.h | 6 +-
> .../media/platform/qcom/iris/iris_platform_gen2.c | 68 ++++++++++
> .../platform/qcom/iris/iris_platform_sm8750.h | 22 ++++
> drivers/media/platform/qcom/iris/iris_probe.c | 4 +
> drivers/media/platform/qcom/iris/iris_vpu3x.c | 146 +++++++++++++++++++++
> drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 +
> drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 +
> 7 files changed, 251 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h
> index adafdce8a856f9c661aabc5ca28f0faceaa93551..fd5a6e69e01cfd00253f4ffb282d40112b93073b 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_common.h
> +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h
> @@ -38,11 +38,15 @@ extern struct iris_platform_data qcs8300_data;
> extern struct iris_platform_data sm8250_data;
> extern struct iris_platform_data sm8550_data;
> extern struct iris_platform_data sm8650_data;
> +extern struct iris_platform_data sm8750_data;
>
> enum platform_clk_type {
> - IRIS_AXI_CLK,
> + IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */
> IRIS_CTRL_CLK,
> IRIS_HW_CLK,
> + IRIS_AXI1_CLK,
> + IRIS_CTRL_FREERUN_CLK,
> + IRIS_HW_FREERUN_CLK,
> };
>
> struct platform_clk_data {
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> index d3026b2bcb708c7ec31f134f628df7e57b54af4f..c7c384fce2332255ea96da69ef4dc0bc1a24771c 100644
> --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c
> @@ -1,6 +1,7 @@
> // SPDX-License-Identifier: GPL-2.0-only
> /*
> * Copyright (c) 2022-2024 Qualcomm Innovation Center, Inc. All rights reserved.
> + * Copyright (c) 2025 Linaro Ltd
I don't see a need to add a copyright here.
> */
>
> #include "iris_core.h"
> @@ -12,6 +13,7 @@
>
> #include "iris_platform_qcs8300.h"
> #include "iris_platform_sm8650.h"
> +#include "iris_platform_sm8750.h"
>
> #define VIDEO_ARCH_LX 1
>
> @@ -463,6 +465,72 @@ struct iris_platform_data sm8650_data = {
> .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl),
> };
>
<snip>
> diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8750.h b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..719056656a5baf48a7bced634d2582629333cf5c
> --- /dev/null
> +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8750.h
> @@ -0,0 +1,22 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2025 Linaro Ltd
Ack.
> static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core)
> {
> @@ -225,6 +230,138 @@ static int iris_vpu33_power_off_controller(struct iris_core *core)
> return 0;
> }
>
<snip>
> +
> +static void iris_vpu35_power_off_hw(struct iris_core *core)
> +{
> + iris_vpu33_power_off_hardware(core);
JFYI, write to AON_WRAPPER_MVP_NOC_LPI_CONTROL before reading the LPI
status was missing in vpu33 along with a retry logic which will be fixed
with
https://lore.kernel.org/linux-media/20250812-sm8650-power-sequence-fix-v1-1-a51e7f99c56c@quicinc.com/
> +
> + iris_disable_unprepare_clock(core, IRIS_HW_FREERUN_CLK);
> + iris_disable_unprepare_clock(core, IRIS_AXI_CLK);
> +}
> +
> +static int iris_vpu35_power_off_controller(struct iris_core *core)
> +{
> + u32 clk_rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
> + u32 val = 0;
> + int ret;
> +
> + writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CPU_CS_X2RPMH);
> +
> + writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> +
> + ret = readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STATUS,
> + val, val & BIT(0), 200, 2000);
> + if (ret)
> + goto disable_power;
> +
> + writel(0x0, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CONTROL);
> +
> + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
Read initial status of AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS
based on value, run the retry loop.
This loop runs till the desired LPI state is reached i.e. BIT(0) is set,
and hardware is idle i.e. BIT(1) or BIT(2) are unset. This suggests a
situation where the hardware might be stuck or slow to transition.
This sequence was not needed for SM8650 since it doesn't have
AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL/STATUS registers.
But required for SM8750, so please add.
> + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_STATUS,
> + val, val & (BIT(0) | BIT(1) | BIT(2)), 15, 1000);
> + if (ret)
> + goto disable_power> +
> + writel(0x0, core->reg_base + AON_WRAPPER_MVP_VIDEO_CTL_NOC_LPI_CONTROL);
> +
> + writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL);
> +
> + ret = readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STATUS,
> + val, val == 0, 200, 2000);
> + if (ret)
> + goto disable_power;
> +
> +disable_power:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK);
> + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> +
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + reset_control_bulk_reset(clk_rst_tbl_size, core->resets);
> +
> + return 0;
> +}
> +
> +static int iris_vpu35_power_on_controller(struct iris_core *core)
> +{
> + u32 rst_tbl_size = core->iris_platform_data->clk_rst_tbl_size;
> + int ret;
> +
> + ret = iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> + if (ret)
> + return ret;
> +
> + ret = reset_control_bulk_reset(rst_tbl_size, core->resets);
> + if (ret)
> + goto err_disable_power;
this reset is not needed to power-on this SOC.
> +
> + ret = iris_prepare_enable_clock(core, IRIS_AXI1_CLK);
> + if (ret)
> + goto err_disable_power;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_FREERUN_CLK);
> + if (ret)
> + goto err_disable_axi1_clk;
> +
> + ret = iris_prepare_enable_clock(core, IRIS_CTRL_CLK);
> + if (ret)
> + goto err_disable_ctrl_free_clk;
> +
> + return 0;
> +
> +err_disable_ctrl_free_clk:
> + iris_disable_unprepare_clock(core, IRIS_CTRL_FREERUN_CLK);
> +err_disable_axi1_clk:
> + iris_disable_unprepare_clock(core, IRIS_AXI1_CLK);
> +err_disable_power:
> + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_POWER_DOMAIN]);
> +
> + return ret;
> +}
> +
Thanks,
Dikshita
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