linux-kernel - Re: [PATCH] spi: spi-qpic-snand: handle 'use_ecc' parameter of qcom_spi_config_cw

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Message-ID: <e5b981f8-9b6b-42c6-b432-537d23f7fd58@gmail.com>
Date: Tue, 12 Aug 2025 13:06:46 +0200
From: Gabor Juhos <j4g8y7@...il.com>
To: Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
 Mark Brown <broonie@...nel.org>
Cc: Md Sadre Alam <quic_mdalam@...cinc.com>,
 Varadarajan Narayanan <quic_varada@...cinc.com>,
 Sricharan Ramabadhran <quic_srichara@...cinc.com>,
 linux-spi@...r.kernel.org, linux-mtd@...ts.infradead.org,
 linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH] spi: spi-qpic-snand: handle 'use_ecc' parameter of
 qcom_spi_config_cw_read()

2025. 08. 12. 11:55 keltezéssel, Konrad Dybcio írta:
> On 8/8/25 7:15 PM, Gabor Juhos wrote:
>> During raw read, neither the status of the ECC correction nor the erased
>> state of the codeword gets checked by the qcom_spi_read_cw_raw() function,
>> so in case of raw access reading the corresponding registers via DMA is
>> superfluous.
>>
>> Extend the qcom_spi_config_cw_read() function to evaluate the existing
>> (but actually unused) 'use_ecc' parameter, and configure reading only
>> the flash status register when ECC is not used.
>>
>> With the change, the code gets in line with the corresponding part of
>> the config_nand_cw_read() function in the qcom_nandc driver.
>>
>> Signed-off-by: Gabor Juhos <j4g8y7@...il.com>
>> ---
>>  drivers/spi/spi-qpic-snand.c | 11 ++++++++---
>>  1 file changed, 8 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
>> index 7b76d2c82a5287df13ee6fcebc4abbe58ca861ee..119003c4784890458a41c67fa8bc17d721030b0d 100644
>> --- a/drivers/spi/spi-qpic-snand.c
>> +++ b/drivers/spi/spi-qpic-snand.c
>> @@ -494,9 +494,14 @@ qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int c
>>  	qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
>>  	qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
>>  
>> -	qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
>> -	qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
>> -			  NAND_BAM_NEXT_SGL);
>> +	if (use_ecc) {
>> +		qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
> 
> Why are we reading 2 registers (the 2 in the func call) here, ...

Because when ECC is used, we need the status of the ECC correction from the
NAND_BUFFER_STATUS register which is placed right after the NAND_FLASH_STATUS.

Here are the relevant definitions from the 'nand-qpic-common.h' header for
reference:

#define	NAND_FLASH_STATUS		0x14
#define	NAND_BUFFER_STATUS		0x18

So the two registers can be read with a single DMA operation.

> ... but 1 everywhere else?

When ECC is not used, we only need the value from the NAND_FLASH_STATUS
register, so we don't have to read two registers.

Regards,
Gabor