| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20250813171136.2213309-1-uwu@icenowy.me> Date: Thu, 14 Aug 2025 01:11:34 +0800 From: Icenowy Zheng <uwu@...nowy.me> To: Drew Fustini <fustini@...nel.org>, Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org> Cc: Michal Wilczynski <m.wilczynski@...sung.com>, Yao Zi <ziyao@...root.org>, Han Gao <rabenda.cn@...il.com>, linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org, Icenowy Zheng <uwu@...nowy.me> Subject: [PATCH 0/2] clk: thead: th1520-ap: allow gate cascade and fix padctrl0 Current ccu_gate implementation does not easily allow gates to be clock parents because of the waste of struct clk_hw in struct ccu_gate; however it's found that the padctrl0 apb clock gate seems to be downstream of perisys-apb4-hclk, gating the latter w/o gating the former makes the padctrl0 registers inaccessible too. Fix this by refactor ccu_gate code, mimicing what Yao Zi did on ccu_mux; and then assign perisys-apb4-hclk as parent of padctrl0 bus gate. This patchset depends on the display clock patchset at [1], although a rebasing to get rid of this dependency is possible. [1] https://lore.kernel.org/linux-riscv/20250813072702.2176993-1-uwu@icenowy.me/ Icenowy Zheng (2): clk: thead: th1520-ap: describe gate clocks with clk_gate clk: thead: th1520-ap: fix parent of padctrl0 clock drivers/clk/thead/clk-th1520-ap.c | 385 +++++++++++++++--------------- 1 file changed, 188 insertions(+), 197 deletions(-) -- 2.50.1
Powered by blists - more mailing lists