[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20250813184701.2444372-3-elder@riscstar.com>
Date: Wed, 13 Aug 2025 13:46:56 -0500
From: Alex Elder <elder@...cstar.com>
To: robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
lpieralisi@...nel.org,
kwilczynski@...nel.org,
mani@...nel.org,
bhelgaas@...gle.com,
vkoul@...nel.org,
kishon@...nel.org
Cc: dlan@...too.org,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
p.zabel@...gutronix.de,
tglx@...utronix.de,
johan+linaro@...nel.org,
thippeswamy.havalige@....com,
namcao@...utronix.de,
mayank.rana@....qualcomm.com,
shradha.t@...sung.com,
inochiama@...il.com,
quic_schintav@...cinc.com,
fan.ni@...sung.com,
devicetree@...r.kernel.org,
linux-phy@...ts.infradead.org,
linux-pci@...r.kernel.org,
spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 2/6] dt-bindings: phy: spacemit: introduce PCIe PHY
Add the Device Tree binding for two PCIe PHYs present on the SpacemiT
K1 SoC. These PHYs are dependent on a separate combo PHY, which
determines at probe time the calibration values used by the PCIe-only
PHYs.
Signed-off-by: Alex Elder <elder@...cstar.com>
---
.../bindings/phy/spacemit,k1-pcie-phy.yaml | 49 +++++++++++++++++++
1 file changed, 49 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
new file mode 100644
index 0000000000000..b0cbd231d9378
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/spacemit,k1-pcie-phy.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/spacemit,k1-pcie-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K1 PCIe PHY
+
+maintainers:
+ - Alex Elder <elder@...cstar.com>
+
+description:
+ There are two PHYs on the SpacemiT K1 SoC used for PCIe (only).
+ These PHYs must be configured using calibration values that are
+ determined by a third "combo PHY". The combo PHY determines
+ these calibration values during probe so they can be used for
+ the two PCIe-only PHYs.
+
+ During normal operation, the PCIe port driver is responsible for
+ ensuring all clocks needed by a PHY are enabled, and all resets
+ affecting the PHY are deasserted.
+
+properties:
+ compatible:
+ const: spacemit,k1-pcie-phy
+
+ reg:
+ items:
+ - description: PHY control registers
+
+ "#phy-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k1-syscon.h>
+ pcie1_phy: phy@...10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0xc0c10000 0x1000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
--
2.48.1
Powered by blists - more mailing lists