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Message-ID: <20250813184701.2444372-7-elder@riscstar.com>
Date: Wed, 13 Aug 2025 13:47:00 -0500
From: Alex Elder <elder@...cstar.com>
To: lpieralisi@...nel.org,
kwilczynski@...nel.org,
mani@...nel.org,
robh@...nel.org,
bhelgaas@...gle.com,
krzk+dt@...nel.org,
conor+dt@...nel.org,
vkoul@...nel.org,
kishon@...nel.org
Cc: dlan@...too.org,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr,
p.zabel@...gutronix.de,
tglx@...utronix.de,
johan+linaro@...nel.org,
thippeswamy.havalige@....com,
namcao@...utronix.de,
mayank.rana@....qualcomm.com,
shradha.t@...sung.com,
inochiama@...il.com,
quic_schintav@...cinc.com,
fan.ni@...sung.com,
devicetree@...r.kernel.org,
linux-phy@...ts.infradead.org,
linux-pci@...r.kernel.org,
spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org
Subject: [PATCH 6/6] riscv: dts: spacemit: PCIe and PHY-related updates
Define PCIe and PHY-related Device Tree nodes for the SpacemiT K1 SoC.
Enable the combo PHY and the two PCIe-only PHYs on the Banana Pi BPI-F3
board. The combo PHY is used for USB on this board, and that will be
enabled when USB 3 support is accepted.
Signed-off-by: Alex Elder <elder@...cstar.com>
---
.../boot/dts/spacemit/k1-bananapi-f3.dts | 28 +++
arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 33 ++++
arch/riscv/boot/dts/spacemit/k1.dtsi | 169 ++++++++++++++++++
3 files changed, 230 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index fe22c747c5012..1c75e38b1fab9 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -40,6 +40,34 @@ &emmc {
status = "okay";
};
+&combo_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie0_3_cfg>;
+ status = "okay";
+};
+
+&pcie1_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie1_3_cfg>;
+ status = "okay";
+};
+
+&pcie2_phy {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pcie2_4_cfg>;
+ status = "okay";
+};
+
+&pcie1 {
+ phys = <&pcie1_phy>;
+ status = "okay";
+};
+
+&pcie2 {
+ phys = <&pcie2_phy>;
+ status = "okay";
+};
+
&uart0 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_2_cfg>;
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
index 3810557374228..e7dbecd7389b7 100644
--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -21,6 +21,39 @@ uart0-2-pins {
};
};
+ pcie0_3_cfg: pcie0-3-cfg {
+ pcie0-3-pins {
+ pinmux = <K1_PADCONF(54, 3)>, /* PERST# */
+ <K1_PADCONF(55, 3)>, /* WAKE */
+ <K1_PADCONF(53, 3)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie1_3_cfg: pcie1-3-cfg {
+ pcie1-3-pins {
+ pinmux = <K1_PADCONF(59, 4)>, /* PERST# */
+ <K1_PADCONF(60, 4)>, /* WAKE */
+ <K1_PADCONF(61, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
+ pcie2_4_cfg: pcie2-4-cfg {
+ pcie2-4-pins {
+ pinmux = <K1_PADCONF(62, 4)>, /* PERST# */
+ <K1_PADCONF(112, 3)>, /* WAKE */
+ <K1_PADCONF(117, 4)>; /* CLKREQ# */
+
+ bias-pull-up = <0>;
+ drive-strength = <21>;
+ };
+ };
+
pwm14_1_cfg: pwm14-1-cfg {
pwm14-1-pins {
pinmux = <K1_PADCONF(44, 4)>;
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
index abde8bb07c95c..6343f6e95284d 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -4,6 +4,8 @@
*/
#include <dt-bindings/clock/spacemit,k1-syscon.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/phy/phy.h>
/dts-v1/;
/ {
@@ -358,6 +360,42 @@ syscon_rcpu2: system-controller@...88000 {
#reset-cells = <1>;
};
+ combo_phy: phy@...10000 {
+ compatible = "spacemit,k1-combo-phy";
+ reg = <0x0 0xc0b10000 0x0 0x1000>;
+ clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+ resets = <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>,
+ <&syscon_apmu RESET_PCIE0_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "global";
+ spacemit,syscon-pmu = <&syscon_apmu>;
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+
+ pcie1_phy: phy@...10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0c10000 0x0 0x1000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ pcie2_phy: phy@...10000 {
+ compatible = "spacemit,k1-pcie-phy";
+ reg = <0x0 0xc0d10000 0x0 0x1000>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
syscon_apbc: system-controller@...15000 {
compatible = "spacemit,k1-syscon-apbc";
reg = <0x0 0xd4015000 0x0 0x1000>;
@@ -814,6 +852,137 @@ pcie-bus {
#size-cells = <2>;
dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>,
<0x0 0xb8000000 0x1 0x38000000 0x3 0x48000000>;
+ pcie0: pcie@...00000 {
+ compatible = "spacemit,k1-pcie-rc";
+ reg = <0x0 0xca000000 0x0 0x00001000>,
+ <0x0 0xca300000 0x0 0x0001ff24>,
+ <0x0 0x8f000000 0x0 0x00002000>,
+ <0x0 0xc0b20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ spacemit,syscon-pmu = <&syscon_apmu 0x03cc>;
+
+ ranges = <0x01000000 0x0 0x8f002000 0 0x8f002000 0x0 0x100000>,
+ <0x02000000 0x0 0x80000000 0 0x80000000 0x0 0x0f000000>;
+
+ clocks = <&syscon_apmu CLK_PCIE0_DBI>,
+ <&syscon_apmu CLK_PCIE0_MASTER>,
+ <&syscon_apmu CLK_PCIE0_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+
+ resets = <&syscon_apmu RESET_PCIE0_DBI>,
+ <&syscon_apmu RESET_PCIE0_MASTER>,
+ <&syscon_apmu RESET_PCIE0_SLAVE>,
+ <&syscon_apmu RESET_PCIE0_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "global";
+
+ interrupts-extended = <&plic 141>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-viewport = <8>;
+
+ status = "disabled";
+ };
+
+ pcie1: pcie@...00000 {
+ compatible = "spacemit,k1-pcie-rc";
+ reg = <0x0 0xca400000 0x0 0x00001000>,
+ <0x0 0xca700000 0x0 0x0001ff24>,
+ <0x0 0x9f000000 0x0 0x00002000>,
+ <0x0 0xc0c20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+ spacemit,syscon-pmu = <&syscon_apmu 0x3d4>;
+
+ ranges = <0x01000000 0x0 0x9f002000 0 0x9f002000 0x0 0x100000>,
+ <0x02000000 0x0 0x90000000 0 0x90000000 0x0 0x0f000000>;
+ clocks = <&syscon_apmu CLK_PCIE1_DBI>,
+ <&syscon_apmu CLK_PCIE1_MASTER>,
+ <&syscon_apmu CLK_PCIE1_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+
+ resets = <&syscon_apmu RESET_PCIE1_DBI>,
+ <&syscon_apmu RESET_PCIE1_MASTER>,
+ <&syscon_apmu RESET_PCIE1_SLAVE>,
+ <&syscon_apmu RESET_PCIE1_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "global";
+
+ interrupts-extended = <&plic 142>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-viewport = <8>;
+
+ status = "disabled";
+ };
+
+ pcie2: pcie@...00000 {
+ compatible = "spacemit,k1-pcie-rc";
+ reg = <0x0 0xca800000 0x0 0x00001000>,
+ <0x0 0xcab00000 0x0 0x0001ff24>,
+ <0x0 0xb7000000 0x0 0x00002000>,
+ <0x0 0xc0d20000 0x0 0x00001000>;
+ reg-names = "dbi",
+ "atu",
+ "config",
+ "link";
+
+ spacemit,syscon-pmu = <&syscon_apmu 0x3dc>;
+
+ ranges = <0x01000000 0x0 0xb7002000 0 0xb7002000 0x0 0x100000>,
+ <0x42000000 0x0 0xa0000000 0 0xa0000000 0x0 0x10000000>,
+ <0x02000000 0x0 0xb0000000 0 0xb0000000 0x0 0x7000000>;
+ clocks = <&syscon_apmu CLK_PCIE2_DBI>,
+ <&syscon_apmu CLK_PCIE2_MASTER>,
+ <&syscon_apmu CLK_PCIE2_SLAVE>;
+ clock-names = "dbi",
+ "mstr",
+ "slv";
+
+ resets = <&syscon_apmu RESET_PCIE2_DBI>,
+ <&syscon_apmu RESET_PCIE2_MASTER>,
+ <&syscon_apmu RESET_PCIE2_SLAVE>,
+ <&syscon_apmu RESET_PCIE2_GLOBAL>;
+ reset-names = "dbi",
+ "mstr",
+ "slv",
+ "global";
+
+ interrupts-extended = <&plic 143>;
+
+ #address-cells = <3>;
+ #size-cells = <2>;
+
+ device_type = "pci";
+ max-link-speed = <2>;
+ bus-range = <0x00 0xff>;
+ num-viewport = <8>;
+
+ status = "disabled";
+ };
};
storage-bus {
--
2.48.1
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