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Message-ID: <20250813072702.2176993-1-uwu@icenowy.me>
Date: Wed, 13 Aug 2025 15:26:59 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Drew Fustini <fustini@...nel.org>,
Guo Ren <guoren@...nel.org>,
Fu Wei <wefu@...hat.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Michal Wilczynski <m.wilczynski@...sung.com>
Cc: Yao Zi <ziyao@...root.org>,
Han Gao <rabenda.cn@...il.com>,
linux-riscv@...ts.infradead.org,
linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org,
Icenowy Zheng <uwu@...nowy.me>
Subject: [PATCH v2 0/3] clk: thead: Changes to TH1520 clock driver for disp
This patchset is my changes to the TH1520 clock driver, mainly for
supporting the display controller.
The first two are functionality additions, with the first one adding
support for enabling/disabling PLLs (for DPU PLL) and the second one
adding support for changing DPU dividers.
The 3rd one is to address hang issues met when testing the DPU driver
w/o clk_ignore_unused command line option.
The 4th patch that used to be in v1 is dropped, makes this patchset
purely display-related.
This patchset has a dependency (a 0th one) [1].
[1] https://lore.kernel.org/linux-riscv/20250809-fix_clocks_thead_aug_9-v1-1-299c33d7a593@samsung.com/
Icenowy Zheng (3):
clk: thead: add support for enabling/disabling PLLs
clk: thead: support changing DPU pixel clock rate
clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL
drivers/clk/thead/clk-th1520-ap.c | 146 +++++++++++++++++++++++-------
1 file changed, 114 insertions(+), 32 deletions(-)
--
2.50.1
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