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Message-ID: <8f7bac84-623b-47dc-bc58-dc0013a85877@riscstar.com>
Date: Thu, 14 Aug 2025 07:30:52 -0500
From: Alex Elder <elder@...cstar.com>
To: Yao Zi <ziyao@...root.org>, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, bhelgaas@...gle.com, vkoul@...nel.org, kishon@...nel.org
Cc: dlan@...too.org, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, alex@...ti.fr, p.zabel@...gutronix.de,
tglx@...utronix.de, johan+linaro@...nel.org, thippeswamy.havalige@....com,
namcao@...utronix.de, mayank.rana@....qualcomm.com, shradha.t@...sung.com,
inochiama@...il.com, quic_schintav@...cinc.com, fan.ni@...sung.com,
devicetree@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-pci@...r.kernel.org, spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo
PHY
On 8/13/25 9:52 PM, Yao Zi wrote:
> On Wed, Aug 13, 2025 at 01:46:55PM -0500, Alex Elder wrote:
>> Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
>> the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual
>> in that only the combo PHY can perform a calibration step needed to
>> determine settings used by the other two PCIe PHYs.
>>
>> Calibration must be done with the combo PHY in PCIe mode, and to allow
>> this to occur independent of the eventual use for the PHY (PCIe or USB)
>> some PCIe-related properties must be supplied: clocks; resets; and a
>> syscon phandle.
>>
>> Signed-off-by: Alex Elder <elder@...cstar.com>
>> ---
>> .../bindings/phy/spacemit,k1-combo-phy.yaml | 110 ++++++++++++++++++
>> 1 file changed, 110 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
>> new file mode 100644
>> index 0000000000000..ed78083a53231
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
>
> ...
>
>> + spacemit,syscon-pmu:
>> + description:
>> + PHandle that refers to the APMU system controller, whose
>> + regmap is used in setting the mode
>> + $ref: /schemas/types.yaml#/definitions/phandle
>
> Clock controllers and ethernet controllers all use spacemit,apmu to
> refer the APMU system controller. Do you think it's better to keep them
> aligned?
I do think it's better to keep them aligned.
And I appreciate your noticing this. I don't see anything
that's accepted upstream that defines properties like this,
but I now see this:
https://lore.kernel.org/lkml/20250812-net-k1-emac-v5-2-dd17c4905f49@iscas.ac.cn/
I did a quick scan for what others do when a property's
value is a phandle, and other than just "syscon" it seems
that word is omitted.
So unless someone else suggests otherwise, I'll use
"spacemit,apmu" for this property in my next version.
> ...
>
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> + - |
>> + #include <dt-bindings/clock/spacemit,k1-syscon.h>
>> + combo_phy: phy@...10000 {
>
> This label is unnecessary.
OK. I used it when testing USB but we can add the label
back when that driver gets reviewed.
>> + compatible = "spacemit,k1-combo-phy";
>> + reg = <0xc0b10000 0x1000>;
>> + clocks = <&syscon_apmu CLK_PCIE0_DBI>,
>> + <&syscon_apmu CLK_PCIE0_MASTER>,
>> + <&syscon_apmu CLK_PCIE0_SLAVE>;
>> + clock-names = "dbi",
>> + "mstr",
>> + "slv";
>> + resets = <&syscon_apmu RESET_PCIE0_DBI>,
>> + <&syscon_apmu RESET_PCIE0_MASTER>,
>> + <&syscon_apmu RESET_PCIE0_SLAVE>,
>> + <&syscon_apmu RESET_PCIE0_GLOBAL>;
>> + reset-names = "dbi",
>> + "mstr",
>> + "slv",
>> + "global";
>> + spacemit,syscon-pmu = <&syscon_apmu>;
>> + #phy-cells = <1>;
>> + status = "disabled";
>> + };
>
> Best regards,
> Yao Zi
Thanks a lot.
-Alex
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