linux-kernel - [PATCH 0/4] Add RZ/G3E GPT clocks and resets

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Message-ID: <20250814124832.76266-1-biju.das.jz@bp.renesas.com>
Date: Thu, 14 Aug 2025 13:48:23 +0100
From: Biju <biju.das.au@...il.com>
To: Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Geert Uytterhoeven <geert+renesas@...der.be>,
	Magnus Damm <magnus.damm@...il.com>
Cc: Biju Das <biju.das.jz@...renesas.com>,
	linux-clk@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	linux-renesas-soc@...r.kernel.org,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	Biju Das <biju.das.au@...il.com>
Subject: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

From: Biju Das <biju.das.jz@...renesas.com>

The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
clocks. The bus clock is module clock and core clock is sourced from
the bus clock. So add support for module clock as parent reusing the
existing rzv2h_cpg_fixed_mod_status_clk_register().

Biju Das (4):
  clk: renesas: rzv2h: Refactor
    rzv2h_cpg_fixed_mod_status_clk_register()
  clk: renesas: rzv2h: Add support for parent mod clocks
  dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
  clk: renesas: r9a09g047: Add GPT clocks and resets

 drivers/clk/renesas/r9a09g047-cpg.c           | 10 ++-
 drivers/clk/renesas/rzv2h-cpg.c               | 74 ++++++++++++-------
 drivers/clk/renesas/rzv2h-cpg.h               | 22 ++++--
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |  2 +
 4 files changed, 75 insertions(+), 33 deletions(-)

-- 
2.43.0