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Message-ID: <aJ1PJBax-Pj983OZ@pie>
Date: Thu, 14 Aug 2025 02:52:03 +0000
From: Yao Zi <ziyao@...root.org>
To: Alex Elder <elder@...cstar.com>, robh@...nel.org, krzk+dt@...nel.org,
conor+dt@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org,
mani@...nel.org, bhelgaas@...gle.com, vkoul@...nel.org,
kishon@...nel.org
Cc: dlan@...too.org, paul.walmsley@...ive.com, palmer@...belt.com,
aou@...s.berkeley.edu, alex@...ti.fr, p.zabel@...gutronix.de,
tglx@...utronix.de, johan+linaro@...nel.org,
thippeswamy.havalige@....com, namcao@...utronix.de,
mayank.rana@....qualcomm.com, shradha.t@...sung.com,
inochiama@...il.com, quic_schintav@...cinc.com, fan.ni@...sung.com,
devicetree@...r.kernel.org, linux-phy@...ts.infradead.org,
linux-pci@...r.kernel.org, spacemit@...ts.linux.dev,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/6] dt-bindings: phy: spacemit: add SpacemiT PCIe/combo
PHY
On Wed, Aug 13, 2025 at 01:46:55PM -0500, Alex Elder wrote:
> Add the Device Tree binding for the PCIe/USB 3.0 combo PHY found in
> the SpacemiT K1 SoC. This is one of three PCIe PHYs, and is unusual
> in that only the combo PHY can perform a calibration step needed to
> determine settings used by the other two PCIe PHYs.
>
> Calibration must be done with the combo PHY in PCIe mode, and to allow
> this to occur independent of the eventual use for the PHY (PCIe or USB)
> some PCIe-related properties must be supplied: clocks; resets; and a
> syscon phandle.
>
> Signed-off-by: Alex Elder <elder@...cstar.com>
> ---
> .../bindings/phy/spacemit,k1-combo-phy.yaml | 110 ++++++++++++++++++
> 1 file changed, 110 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
> new file mode 100644
> index 0000000000000..ed78083a53231
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/spacemit,k1-combo-phy.yaml
...
> + spacemit,syscon-pmu:
> + description:
> + PHandle that refers to the APMU system controller, whose
> + regmap is used in setting the mode
> + $ref: /schemas/types.yaml#/definitions/phandle
Clock controllers and ethernet controllers all use spacemit,apmu to
refer the APMU system controller. Do you think it's better to keep them
aligned?
...
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/spacemit,k1-syscon.h>
> + combo_phy: phy@...10000 {
This label is unnecessary.
> + compatible = "spacemit,k1-combo-phy";
> + reg = <0xc0b10000 0x1000>;
> + clocks = <&syscon_apmu CLK_PCIE0_DBI>,
> + <&syscon_apmu CLK_PCIE0_MASTER>,
> + <&syscon_apmu CLK_PCIE0_SLAVE>;
> + clock-names = "dbi",
> + "mstr",
> + "slv";
> + resets = <&syscon_apmu RESET_PCIE0_DBI>,
> + <&syscon_apmu RESET_PCIE0_MASTER>,
> + <&syscon_apmu RESET_PCIE0_SLAVE>,
> + <&syscon_apmu RESET_PCIE0_GLOBAL>;
> + reset-names = "dbi",
> + "mstr",
> + "slv",
> + "global";
> + spacemit,syscon-pmu = <&syscon_apmu>;
> + #phy-cells = <1>;
> + status = "disabled";
> + };
Best regards,
Yao Zi
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