linux-kernel - Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for x1e80100 GPU

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Message-ID: <1727374d-0461-4442-ab35-9acb8ef7f666@oss.qualcomm.com>
Date: Thu, 14 Aug 2025 22:08:26 +0530
From: Akhil P Oommen <akhilpo@....qualcomm.com>
To: Neil Armstrong <neil.armstrong@...aro.org>,
        Konrad Dybcio <konrad.dybcio@....qualcomm.com>,
        Rob Clark <robin.clark@....qualcomm.com>, Sean Paul <sean@...rly.run>,
        Konrad Dybcio <konradybcio@...nel.org>,
        Dmitry Baryshkov <lumag@...nel.org>,
        Abhinav Kumar <abhinav.kumar@...ux.dev>,
        Jessica Zhang <jessica.zhang@....qualcomm.com>,
        Marijn Suijten <marijn.suijten@...ainline.org>,
        David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
        freedreno@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
        Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
Subject: Re: [PATCH v2] drm/msm: adreno: a6xx: enable GMU bandwidth voting for
 x1e80100 GPU

On 8/14/2025 7:56 PM, Neil Armstrong wrote:
> Hi,
> 
> On 14/08/2025 13:22, Konrad Dybcio wrote:
>> On 8/14/25 1:21 PM, Konrad Dybcio wrote:
>>> On 7/31/25 12:19 PM, Konrad Dybcio wrote:
>>>> On 7/25/25 10:35 AM, Neil Armstrong wrote:
>>>>> The Adreno GPU Management Unit (GMU) can also scale DDR Bandwidth
>>>>> along
>>>>> the Frequency and Power Domain level, but by default we leave the
>>>>> OPP core scale the interconnect ddr path.
>>>>>
>>>>> Declare the Bus Control Modules (BCMs) and the corresponding
>>>>> parameters
>>>>> in the GPU info struct to allow the GMU to vote for the bandwidth.
>>>>>
>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@....qualcomm.com>
>>>>> Signed-off-by: Neil Armstrong <neil.armstrong@...aro.org>
>>>>> ---
>>>>> Changes in v2:
>>>>> - Used proper ACV perfmode bit/freq
>>>>> - Link to v1: https://lore.kernel.org/r/20250721-topic-x1e80100-
>>>>> gpu-bwvote-v1-1-946619b0f73a@...aro.org
>>>>> ---
>>>>>   drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 11 +++++++++++
>>>>>   1 file changed, 11 insertions(+)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/
>>>>> gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> index
>>>>> 00e1afd46b81546eec03e22cda9e9a604f6f3b60..892f98b1f2ae582268adebd758437ff60456cdd5 100644
>>>>> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
>>>>> @@ -1440,6 +1440,17 @@ static const struct adreno_info a7xx_gpus[] = {
>>>>>               .pwrup_reglist = &a7xx_pwrup_reglist,
>>>>>               .gmu_chipid = 0x7050001,
>>>>>               .gmu_cgc_mode = 0x00020202,
>>>>> +            .bcms = (const struct a6xx_bcm[]) {
>>>>> +                { .name = "SH0", .buswidth = 16 },
>>>>> +                { .name = "MC0", .buswidth = 4 },
>>>>> +                {
>>>>> +                    .name = "ACV",
>>>>> +                    .fixed = true,
>>>>> +                    .perfmode = BIT(3),
>>>>> +                    .perfmode_bw = 16500000,
>>>>
>>>> Reviewed-by: Konrad Dybcio <konrad.dybcio@....qualcomm.com>
>>>
>>> Actually no, BIT(3) is for the CPU (OS), GPU should use BIT(2)

You are right that BIT(2) is GPU specific, but that support was
commercialized from A7XX_GEN3. Anyway, the Win KMD uses BIT(2), so lets
use that in Linux too.

I know some docs show BIT(2) support, but lets not bring in untested
configurations.

-Akhil.

>>
>> This is *very* platform-dependent, goes without saying..
>>
>> I see BIT(2) is also valid for X1P4
> 
> 
> I'm confused, Akhil can you confirm ?
> 
> Neil>
>>
>> Konrad
>