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Message-ID: <20250814-refreshing-watchful-lemming-4feb03@kuoka>
Date: Thu, 14 Aug 2025 10:13:35 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Shradha Todi <shradha.t@...sung.com>
Cc: linux-pci@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org, 
	linux-phy@...ts.infradead.org, mani@...nel.org, lpieralisi@...nel.org, kwilczynski@...nel.org, 
	robh@...nel.org, bhelgaas@...gle.com, jingoohan1@...il.com, krzk+dt@...nel.org, 
	conor+dt@...nel.org, alim.akhtar@...sung.com, vkoul@...nel.org, kishon@...nel.org, 
	arnd@...db.de, m.szyprowski@...sung.com, jh80.chung@...sung.com, 
	pankaj.dubey@...sung.com
Subject: Re: [PATCH v3 08/12] dt-bindings: phy: Add PCIe PHY support for FSD
 SoC

On Mon, Aug 11, 2025 at 09:16:34PM +0530, Shradha Todi wrote:
> Since Tesla FSD SoC uses Samsung PCIe PHY, add support in
> exynos PCIe PHY bindings.
> 
> In Tesla FSD SoC, the two PHY instances, although having identical
> hardware design and register maps, are placed in different locations
> (Placement and routing) inside the SoC and have distinct
> PHY-to-Controller topologies. (One instance is connected to two PCIe
> controllers, while the other is connected to only one). As a result,
> they experience different analog environments, including varying
> channel losses and noise profiles.
> 
> Since these PHYs lack internal adaptation mechanisms and f/w based
> tuning, manual register programming is required for analog tuning.
> To ensure optimal signal integrity, it is essential to use different
> register values for each PHY instance, despite their identical hardware
> design. This is because the same register values may not be suitable
> for both instances due to their differing environments and topologies.

Would be nice if above (or most of it) would be reflected in binding
description. Please do so and:

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>

Best regards,
Krzysztof


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