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Message-Id: <20250814084218.1171386-2-tmaimon77@gmail.com>
Date: Thu, 14 Aug 2025 11:42:17 +0300
From: Tomer Maimon <tmaimon77@...il.com>
To: robh+dt@...nel.org,
krzysztof.kozlowski+dt@...aro.org,
conor+dt@...nel.org,
avifishman70@...il.com,
tali.perry1@...il.com,
joel@....id.au,
venture@...gle.com,
yuenn@...gle.com,
benjaminfair@...gle.com
Cc: openbmc@...ts.ozlabs.org,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Tomer Maimon <tmaimon77@...il.com>
Subject: [PATCH v2 1/2] arm64: dts: nuvoton: combine NPCM845 reset and clk nodes
Combine the NPCM845 reset and clock controller nodes into a single node
with compatible "nuvoton,npcm845-reset" in nuvoton-common-npcm8xx.dtsi,
using the auxiliary device framework to provide clock functionality.
Update the register range to 0xC4 to cover the shared reset and clock
registers at 0xf0801000.
Remove the separate nuvoton,npcm845-clk node, as the reset driver now
handles clocks via an auxiliary device.
Signed-off-by: Tomer Maimon <tmaimon77@...il.com>
---
.../boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi | 11 +++--------
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
index acd3137d2464..e4053ffefe90 100644
--- a/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
+++ b/arch/arm64/boot/dts/nuvoton/nuvoton-common-npcm8xx.dtsi
@@ -42,17 +42,12 @@ ahb {
interrupt-parent = <&gic>;
ranges;
- rstc: reset-controller@...01000 {
+ clk: rstc: reset-controller@...01000 {
compatible = "nuvoton,npcm845-reset";
- reg = <0x0 0xf0801000 0x0 0x78>;
- #reset-cells = <2>;
+ reg = <0x0 0xf0801000 0x0 0xC4>;
nuvoton,sysgcr = <&gcr>;
- };
-
- clk: clock-controller@...01000 {
- compatible = "nuvoton,npcm845-clk";
+ #reset-cells = <2>;
#clock-cells = <1>;
- reg = <0x0 0xf0801000 0x0 0x1000>;
};
apb {
--
2.34.1
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