linux-kernel - Re: Re: [PATCH v1 1/2] dt-bindings: sata: eswin: Document for EIC7700 SoC

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Message-ID: <2630d08e.133.198a7fe5583.Coremail.luyulin@eswincomputing.com>
Date: Thu, 14 Aug 2025 17:51:59 +0800 (GMT+08:00)
From: luyulin@...incomputing.com
To: "Niklas Cassel" <cassel@...nel.org>
Cc: hehuan1@...incomputing.com, dlemoal@...nel.org, robh@...nel.org,
	krzk+dt@...nel.org, conor+dt@...nel.org, linux-ide@...r.kernel.org,
	devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
	p.zabel@...gutronix.de, ningyu@...incomputing.com,
	linmin@...incomputing.com, "Serge Semin" <fancer.lancer@...il.com>
Subject: Re: Re: [PATCH v1 1/2] dt-bindings: sata: eswin: Document for
 EIC7700 SoC

Hi Niklas,

Thank you very much for your constructive suggestions. Based on your advice,
I have optimized both the driver and the YAML program.
I sincerely apologize for the delayed response to your suggestions.
During this period, we have carefully studied the kernel specifications
and slowed down the pace of submitting patches.
> 
> Hello Huan He,
> 
> On Thu, May 15, 2025 at 04:57:23PM +0800, hehuan1@...incomputing.com wrote:
> > From: Huan He <hehuan1@...incomputing.com>
> > 
> > Add eic7700 AHCI SATA controller device with single port support.
> > For the eic7700 SATA registers, it supports AHCI standard interface,
> > interrupt modes (INTx/MSI/PME), APB reset control,
> > and HSP_SP_CSR register configuration.
> > 
> > Co-developed-by: Yulin Lu <luyulin@...incomputing.com>
> > Signed-off-by: Yulin Lu <luyulin@...incomputing.com>
> > Signed-off-by: Huan He <hehuan1@...incomputing.com>
> > ---
> >  .../bindings/ata/eswin,eic7700-sata.yaml      | 80 +++++++++++++++++++
> >  1 file changed, 80 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-sata.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/ata/eswin,eic7700-sata.yaml b/Documentation/devicetree/bindings/ata/eswin,eic7700-sata.yaml
> > new file mode 100644
> > index 000000000000..71e1b865ed2a
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/ata/eswin,eic7700-sata.yaml
> > @@ -0,0 +1,80 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/ata/eswin,eic7700-sata.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: Eswin EIC7700 SoC SATA Controller
> > +
> > +maintainers:
> > +  - Yulin Lu <luyulin@...incomputing.com>
> > +  - Huan He <hehuan1@...incomputing.com>
> > +
> > +description: |
> > +  This binding describes the SATA controller integrated in the Eswin EIC7700 SoC.
> > +  The controller is compatible with the AHCI (Advanced Host Controller Interface)
> > +  specification and supports up to 1 port.
> > +
> > +properties:
> > +  compatible:
> > +    const: eswin,eic7700-ahci
> > +
> > +  reg:
> > +    maxItems: 1
> > +    description: Address range of the SATA registers
> > +
> > +  interrupt-names:
> > +    items:
> > +      - const: intrq
> > +      - const: msi
> > +      - const: pme
> > +
> > +  interrupts:
> > +    maxItems: 3
> > +    description: The SATA interrupt numbers
> > +
> > +  ports-implemented:
> > +    maximum: 0x1
> > +
> > +  resets:
> > +    maxItems: 1
> > +    description: resets to be used by the controller.
> > +
> > +  reset-names:
> > +    const: apb
> > +
> > +  '#address-cells':
> > +    const: 2
> > +
> > +  '#size-cells':
> > +    const: 2
> > +
> > +  eswin,hsp_sp_csr:
> > +    $ref: /schemas/types.yaml#/definitions/phandle-array
> > +    description: hsp_sp_csr regs to be used by the controller.
> > +
> > +required:
> > +  - compatible
> > +  - reg
> > +  - interrupt-names
> > +  - interrupts
> > +  - resets
> > +  - reset-names
> > +  - eswin,hsp_sp_csr
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > +  - |
> > +    sata: sata@...20000 {
> > +      compatible = "eswin,eic7700-ahci";
> > +      reg = <0x50420000 0x10000>;
> > +      interrupt-parent = <&plic>;
> > +      interrupt-names = "intrq", "msi", "pme";
> > +      interrupts = <58>, <59>, <60>;
> > +      ports-implemented = <0x1>;
> > +      resets = <&reset 7 (1 << 27)>;
> > +      reset-names = "apb";
> > +      #size-cells = <2>;
> > +      eswin,hsp_sp_csr = <&hsp_sp_csr 0x1050>;
> > +    };
> > -- 
> > 2.25.1
> > 
> 
> I'm surprised that you AHCI controller does not need any clocks ;)
> 
> 
> When looking at the EIC7700X TRM:
> https://github.com/eswincomputing/EIC7700X-SoC-Technical-Reference-Manual/releases/download/v1.0.0-20250103/EIC7700X_SoC_Technical_Reference_Manual_Part2.pdf
> 
> It is obvious that this SoC integrates the DWC AHCI controller.
> 
> Thus, I would have expected your DT binding to have a:
> $ref: snps,dwc-ahci-common.yaml#
> 
> Please have a look at these bindings:
> baikal,bt1-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
> baikal,bt1-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
> rockchip,dwc-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
> rockchip,dwc-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
> snps,dwc-ahci-common.yaml:$id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
> snps,dwc-ahci.yaml:  - $ref: snps,dwc-ahci-common.yaml#
> snps,dwc-ahci.yaml:    $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
> 
> The good news is that snps,dwc-ahci-common.yaml has defined and documented
> all the SATA clocks and resets for your board already (a lot of them which
> you missed to include in this binding).
> 
> 
> Looking quickly at:
> eswin,hsp_sp_csr = <&hsp_sp_csr 0x1050>;
> 
> I can't help to wonder if these regs shouldn't be in a SATA PHY binding
> instead.
> 
> Do e.g. a
> $ git grep -A 20 snps,dwc-ahci arch/
> 
> There are multiple examples that use a PHY driver.
> 
> If you were to implement a PHY driver, it is possible that you would
> not need to create a new (AHCI) DT binding at all, you could probably
> just add your compatible string to snps,dwc-ahci.yaml, as (from a quick)
> glance, all the only platform specific things appear to be PHY related.
> 
Thank you very much for your expert advice. I have already implemented a 
independent PHY driver, while the controller driver utilizes ahci_dwc.c.
Due to our hardware platform's SATA controller has specific constraints on clock, reset
and port resources, I think adding these to snps,dwc-ahci.yaml might compromise its readability.
Following reference implementations from other vendors in the Linux kernel, 
such as rockchip,dwc-ahci.yaml, amlogic,axg-pcie.yaml and others, I plan to create 
a new eswin,eic7700-ahci.yaml to describe these specifications.
Based on your professional experience, would you consider this approach acceptable?

Best regards,
Yulin