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Message-ID: <074b6da4-ea61-453a-a398-608cf7750251@linaro.org>
Date: Fri, 15 Aug 2025 13:33:43 +0100
From: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
To: Wenmeng Liu <quic_wenmliu@...cinc.com>,
Loic Poulain <loic.poulain@....qualcomm.com>, Robert Foss
<rfoss@...nel.org>, Andi Shyti <andi.shyti@...nel.org>,
Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>, Bjorn Andersson <andersson@...nel.org>,
Konrad Dybcio <konradybcio@...nel.org>, vladimir.zapolskiy@...aro.org,
todor.too@...il.com
Cc: linux-i2c@...r.kernel.org, linux-arm-msm@...r.kernel.org,
devicetree@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-media@...r.kernel.org
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sa8775p: Add CCI definitions
On 15/08/2025 08:07, Wenmeng Liu wrote:
> Qualcomm SA8775P SoC contains 4 Camera Control Interface controllers.
>
> Signed-off-by: Wenmeng Liu <quic_wenmliu@...cinc.com>
> ---
> arch/arm64/boot/dts/qcom/lemans.dtsi | 268 +++++++++++++++++++++++++++++++++++
> 1 file changed, 268 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi
> index 67d1e293861970e9ddfc0df1bb674aeffb6bee6f..ba2715eee4fbf705b790a46c3b09eb20007b32b5 100644
> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
> @@ -4358,6 +4358,162 @@ videocc: clock-controller@...0000 {
> #power-domain-cells = <1>;
> };
>
> + cci0: cci@...3000 {
> + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac13000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_0_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + pinctrl-0 = <&cci0_0_default &cci0_1_default>;
> + pinctrl-1 = <&cci0_0_sleep &cci0_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci0_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci0_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci1: cci@...4000 {
> + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac14000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_1_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + pinctrl-0 = <&cci1_0_default &cci1_1_default>;
> + pinctrl-1 = <&cci1_0_sleep &cci1_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci1_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci1_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci2: cci@...5000 {
> + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac15000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 651 IRQ_TYPE_EDGE_RISING>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_2_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + pinctrl-0 = <&cci2_0_default &cci2_1_default>;
> + pinctrl-1 = <&cci2_0_sleep &cci2_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci2_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci2_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> + cci3: cci@...6000 {
> + compatible = "qcom,sa8775p-cci", "qcom,msm8996-cci";
> + reg = <0x0 0x0ac16000 0x0 0x1000>;
> +
> + interrupts = <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>;
> +
> + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
> +
> + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>,
> + <&camcc CAM_CC_CPAS_AHB_CLK>,
> + <&camcc CAM_CC_CCI_3_CLK>;
> + clock-names = "camnoc_axi",
> + "cpas_ahb",
> + "cci";
> +
> + pinctrl-0 = <&cci3_0_default &cci3_1_default>;
> + pinctrl-1 = <&cci3_0_sleep &cci3_1_sleep>;
> + pinctrl-names = "default", "sleep";
> +
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + status = "disabled";
> +
> + cci3_i2c0: i2c-bus@0 {
> + reg = <0>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + cci3_i2c1: i2c-bus@1 {
> + reg = <1>;
> + clock-frequency = <1000000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> + };
> +
> camss: isp@...8000 {
> compatible = "qcom,sa8775p-camss";
>
> @@ -5189,6 +5345,118 @@ tlmm: pinctrl@...0000 {
> gpio-ranges = <&tlmm 0 0 149>;
> wakeup-parent = <&pdc>;
>
> + cci0_0_default: cci0-0-default-state {
> + pins = "gpio60", "gpio61";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci0_0_sleep: cci0-0-sleep-state {
> + pins = "gpio60", "gpio61";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci0_1_default: cci0-1-default-state {
> + pins = "gpio52", "gpio53";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci0_1_sleep: cci0-1-sleep-state {
> + pins = "gpio52", "gpio53";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci1_0_default: cci1-0-default-state {
> + pins = "gpio62", "gpio63";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci1_0_sleep: cci1-0-sleep-state {
> + pins = "gpio62", "gpio63";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci1_1_default: cci1-1-default-state {
> + pins = "gpio54", "gpio55";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci1_1_sleep: cci1-1-sleep-state {
> + pins = "gpio54", "gpio55";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci2_0_default: cci2-0-default-state {
> + pins = "gpio64", "gpio65";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci2_0_sleep: cci2-0-sleep-state {
> + pins = "gpio64", "gpio65";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci2_1_default: cci2-1-default-state {
> + pins = "gpio56", "gpio57";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci2_1_sleep: cci2-1-sleep-state {
> + pins = "gpio56", "gpio57";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci3_0_default: cci3-0-default-state {
> + pins = "gpio66", "gpio67";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci3_0_sleep: cci3-0-sleep-state {
> + pins = "gpio66", "gpio67";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> + cci3_1_default: cci3-1-default-state {
> + pins = "gpio58", "gpio59";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-up = <2200>;
> + };
> +
> + cci3_1_sleep: cci3-1-sleep-state {
> + pins = "gpio58", "gpio59";
> + function = "cci_i2c";
> + drive-strength = <2>;
> + bias-pull-down;
> + };
> +
> qup_i2c0_default: qup-i2c0-state {
> pins = "gpio20", "gpio21";
> function = "qup0_se0";
>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@...aro.org>
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