linux-kernel - [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8 switchboard

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Message-Id: <20250815-mgx4u_devicetree-v1-2-66db6fa5a7e4@nvidia.com>
Date: Fri, 15 Aug 2025 12:45:56 -0700
From: Marc Olberding <molberding@...dia.com>
To: Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, 
 Conor Dooley <conor+dt@...nel.org>, Joel Stanley <joel@....id.au>, 
 Andrew Jeffery <andrew@...econstruct.com.au>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
 linux-aspeed@...ts.ozlabs.org, linux-kernel@...r.kernel.org, 
 Marc Olberding <molberding@...dia.com>
Subject: [PATCH 2/3] ARM: dts: aspeed: Add device tree includes for the cx8
 switchboard

The mgx cx8 switchboard is used to network mgx GPUs

Signed-off-by: Marc Olberding <molberding@...dia.com>
---
 .../dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi    | 80 ++++++++++++++++++++++
 .../dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi    | 80 ++++++++++++++++++++++
 2 files changed, 160 insertions(+)

diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..051c8cf0b7d12b1fa4c84db896ca480b21627e23
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-north.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX0", "RST_SEQ_CX0_L",
+			  "BOOT_COMPLT_CX0", "FNP_CX0_L",
+			  "WP_FRU_CX0", "OVT_SHUTDOWN_CX0",
+			  "", "",
+			  "", "",
+			  "TMP_WARNING_CX0", "USB_HUB1_RST_L",
+			  "I2C_SWITCH1_RESET", "MCU1_GPIO",
+			  "MCU1_RST_N", "MCU1_RECOVERY_N";
+
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+
diff --git a/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
new file mode 100644
index 0000000000000000000000000000000000000000..cc8e71f374e100ba7f977138a21ea27a83ca36ed
--- /dev/null
+++ b/arch/arm/boot/dts/aspeed/nvidia-mgx-cx8-switch-south.dtsi
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+// Copyright 2025 Nvidia
+
+eeprom@56 {
+	compatible = "atmel,24c128";
+	reg = <0x56>;
+};
+
+gpio@26 {
+	compatible = "nxp,pca9555";
+	reg = <0x26>;
+	gpio-controller;
+	#gpio-cells = <2>;
+	gpio-line-names = "WP_QSPI_CX1", "RST_SEQ_CX1_L",
+			  "BOOT_CMPLT_CX1", "FNP_CX1_L",
+			  "WP_FRU_CX1", "OVT_SHUTDOWN_CX1",
+			  "TMP_WARNING_CX1", "USB_HUB2_RST_L",
+			  "I2C_SWITCH2_RESET", "",
+			  "", "",
+			  "", "",
+			  "", "";
+};
+
+i2c-mux@72 {
+	compatible = "nxp,pca9546";
+	reg = <0x72>;
+	i2c-mux-idle-disconnect;
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	i2c@0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <0>;
+	};
+	i2c@1 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <1>;
+	};
+	i2c@2 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <2>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+	i2c@3 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		reg = <3>;
+		gpio@20 {
+			reg = <0x20>;
+			gpio-controller;
+			compatible = "nxp,pca6408";
+			#gpio-cells = <2>;
+			gpio-line-names = "GLOBAL_WP", "OOB_RST_N",
+					  "OOB_RECOVERY", "MCU_RECOVERY_N",
+					  "MCU_RST_N", "MCU_BYPASS_N",
+					  "SMBUS_FRU_EEPROM_WP", "";
+		};
+		eeprom@50 {
+			reg = <0x50>;
+			compatible = "atmel,24c128";
+		};
+	};
+};
+

-- 
2.34.1