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Message-ID:
<SY4P282MB30630DE6D63A24ED9BF3E30EC534A@SY4P282MB3063.AUSP282.PROD.OUTLOOK.COM>
Date: Fri, 15 Aug 2025 11:53:51 +1000
From: Stephen Horvath <s.horvath@...look.com.au>
To: Borislav Petkov <bp@...en8.de>
Cc: Thomas Gleixner <tglx@...utronix.de>, Ingo Molnar <mingo@...hat.com>,
Dave Hansen <dave.hansen@...ux.intel.com>, "H. Peter Anvin" <hpa@...or.com>,
"x86@...nel.org" <x86@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH] x86/tsc: Read AMD CPU frequency from
Core::X86::Msr::PStateDef
Hi Borislav, Thank you very much for reviewing my patch!
On 15/8/25 01:25, Borislav Petkov wrote:
> On Wed, Aug 13, 2025 at 11:23:38AM +0000, Stephen Horvath wrote:
>> + /* The PPR defines the core multiplier as CpuFid * 25MHz */
>> + p0_freq = cpufid * 25;
>
> As someone already pointed out:
Was this pointed out publicly, or something internally? I couldn't find
any relevant TSC patches for AMD on lore when I looked previously (other
than the Secure TSC which didn't seem applicable).
>
> PPR Vol 1 for AMD Family 1Ah Model 02h C1
>
> ...
>
> MSRC001_006[4...B] [P-state [7:0]] (Core::X86::Msr::PStateDef)
>
> ...
>
> CpuFid[11:0]: core frequency ID.
>
> FFFh- <Value>*5
> 010h
>
> So we need to do per-family checks here.
Ah, good catch! I did check through the 17h and 19h PPRs, but overlooked
1Ah. At least 1Ah is simpler since there's no divisor.
>
> Not sure if that is worth it, frankly.
>
Yeah that's fair enough. I might submit a v2 with some changes next week
and leave it at that, depending on feedback from others.
Thank you again for your time reviewing this!
Steve.
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