Message-ID: <20250815235552.969779-1-korakit@google.com>
Date: Fri, 15 Aug 2025 23:55:52 +0000
From: Korakit Seemakhupt <korakit@...gle.com>
To: binbin.wu@...ux.intel.com
Cc: bp@...en8.de, dave.hansen@...ux.intel.com, dionnaglaze@...gle.com, 
	hpa@...or.com, jgross@...e.com, jiewen.yao@...el.com, jxgao@...gle.com, 
	kirill.shutemov@...ux.intel.com, kvm@...r.kernel.org, 
	linux-kernel@...r.kernel.org, mingo@...hat.com, nik.borisov@...e.com, 
	pbonzini@...hat.com, pgonda@...gle.com, rick.p.edgecombe@...el.com, 
	seanjc@...gle.com, tglx@...utronix.de, thomas.lendacky@....com, 
	vkuznets@...hat.com, x86@...nel.org, vannapurve@...gle.com
Subject: Re: [PATCH 0/2] x86/kvm: Force legacy PCI hole as WB under SNP/TDX

>> On 5/28/2025 11:33 PM, Sean Christopherson wrote:
>>
>> Summary, with the questions at the end.
>>
>> Recent upstream kernels running in GCE SNP/TDX VMs fail to probe the TPM due to
>> the TPM driver's ioremap (with UC) failing because the kernel has already mapped
>> the range using a cachaeable mapping (WB).
>>
>>   ioremap error for 0xfed40000-0xfed45000, requested 0x2, got 0x0
>>   tpm_tis MSFT0101:00: probe with driver tpm_tis failed with error -12
>>
>> The "guilty" commit is 8e690b817e38 ("x86/kvm: Override default caching mode for
>> SEV-SNP and TDX"), which as the subject suggests, forces the kernel's MTRR memtype
>> to WB.  With SNP and TDX, the virtual MTRR state is (a) controlled by the VMM and
>> thus is untrusted, and (b) _should_ be irrelevant because no known hypervisor
>> actually honors the memtypes programmed into the virtual MTRRs.
>>
>> It turns out that the kernel has been relying on the MTRRs to force the TPM TIS
>> region (and potentially other regions) to be UC, so that the kernel ACPI driver's
>> attempts to map of SystemMemory entries as cacheable get forced to UC.  With MTRRs
>> forced WB, x86_acpi_os_ioremap() succeeds in creating a WB mapping, which in turn
>> causes the ioremap infrastructure to reject the TPM driver's UC mapping.
>>
>> IIUC, the TPM entry(s) in the ACPI tables for GCE VMs are derived (built?) from
>> EDK2's TPM ASL.  And (again, IIUC), this code in SecurityPkg/Tcg/Tcg2Acpi/Tpm.asl[1]
>>
>>        //
>>        // Operational region for TPM access
>>        //
>>        OperationRegion (TPMR, SystemMemory, 0xfed40000, 0x5000)
>>
>> generates the problematic SystemMemory entry that triggers the ACPI driver's
>> auto-mapping logic.
>>
>> QEMU-based VMs don't suffer the same fate, as QEMU intentionally[2] doesn't use
>> EDK2's AML for the TPM, and QEMU doesn't define a SystemMemory entry, just a
>> Memory32Fixed entry.
>>
>> Presumably this an EDK2 bug?  If it's not an EDK2 bug, then how is the kernel's
>> ACPI driver supposed to know that some ranges of SystemMemory must be mapped UC?
> 
> On 7/30/2025 3:34 PM, Binbin Wu: Wrote
> 
> According to the ACPI spec 6.6, an operation region of SystemMemory has no
> interface to specify the cacheable attribute.
> 
> One solution could be using MTRRs to communicate the memory attribute of legacy
> PCI hole to the kernel. But during the PUCK meeting last week, Sean mentioned
> that "long-term, firmware should not be using MTRRs to communicate anything to
> the kernel." So this solution is not preferred.
> 
> If not MTRRs, there should be an alternative way to do the job.
> 1. ACPI table
>     According to the ACPI spec, neither operation region nor 32-Bit Fixed Memory
>     Range Descriptor can specify the cacheable attribute.
>     "Address Space Resource Descriptors" could be used to describe a memory range
>     and the they can specify the cacheable attribute via "Type Specific Flags".
>     One of the Address Space Resource Descriptors could be added to the ACPI
>     table as a hint when the kernel do the mapping for operation region.
>     (There is "System Physical Address (SPA) Range Structure", which also can
>     specify the cacheable attribute. But it's should be used for NVDIMMs.)
> 2. EFI memory map descriptor
>     EFI memory descriptor can specify the cacheable attribute. Firmware can add
>     a EFI memory descriptor for the TPM TIS device as a hint when the kernel do
>     the mapping for operation region.
> 
> Operation region of SystemMemory is still needed if a "Control Method" of APCI
> needs to access a field, e.g., the method _STA. Checking another descriptor for
> cacheable attribute, either "Address Space Resource Descriptor" or "EFI memory
> map descriptor" during the ACPI code doing the mapping for operation region
> makes the code complicated.
> 
> Another thing is if long-term firmware should not be using MTRRs to to
> communicate anything to the kernel. It seems it's safer to use ioremap() instead
> of ioremap_cache() for MMIO resource when the kernel do the mapping for the
> operation region access?

Even after changing the ACPI memory resource descriptor from 32-Bit Fixed 
Memory to DWordMemory with caching parameter set to uncached, the ACPI stack still 
tries to ioremap the memory as cachable. 

However, forcing the Operation Region to be PCI_Config instead of SystemMemory 
in the ACPI table seems to allow the vTPM device initilization to succeed as 
it avoids the vTPM region from getting ioremapped by the ACPI stack.

We have also verified that forcing the ACPI stack to use ioremap() instead of 
ioremap_cache() also allows vTPM to initialize properly. The reference change 
I made is below.

diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index dae6a73be40e..2771d3f66d0a 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -1821,7 +1821,7 @@ u64 x86_default_get_root_pointer(void)
 #ifdef CONFIG_XEN_PV
 void __iomem *x86_acpi_os_ioremap(acpi_physical_address phys, acpi_size size)
 {
-       return ioremap_cache(phys, size);
+       return ioremap(phys, size);
 }

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