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Message-ID: <92e57929-a978-4d5f-97d4-b7779736d0db@ti.com>
Date: Fri, 15 Aug 2025 08:05:20 +0530
From: "Kumar, Udit" <u-kumar1@...com>
To: Beleswar Padhi <b-padhi@...com>, <nm@...com>, <vigneshr@...com>,
<kristo@...nel.org>, <robh@...nel.org>, <krzk+dt@...nel.org>,
<conor+dt@...nel.org>
CC: <afd@...com>, <hnagalla@...com>, <jm@...com>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>, <linux-arm-kernel@...ts.infradead.org>,
<u-kumar1@...com>
Subject: Re: [PATCH 03/33] Revert "arm64: dts: ti: k3-j721e-sk: Fix reversed
C6x carveout locations"
On 8/15/2025 4:08 AM, Beleswar Padhi wrote:
> This reverts commit 9f3814a7c06b7c7296cf8c1622078ad71820454b.
>
> The C6x carveouts are reversed intentionally. This is due to the
> requirement to keep the DMA memory region as non-cached, however the
> minimum granular cache region for C6x is 16MB. So, C66x_0 marks the
> entire C66x_1 16MB memory carveouts as non-cached, and uses the DMA
> memory region of C66x_1 as its own, and vice-versa.
Sorry , but i failed to understand how this swap helps in making region
non-cached.
16MB logic is understood.
>
> This was also called out in the original commit which introduced these
> reversed carveouts:
> "The minimum granularity on the Cache settings on C66x DSP cores
> is 16MB, so the DMA memory regions are chosen such that they are
> in separate 16MB regions for each DSP, while reserving a total
> of 16 MB for each DSP and not changing the overall DSP
> remoteproc carveouts."
>
> Fixes: 9f3814a7c06b ("arm64: dts: ti: k3-j721e-sk: Fix reversed C6x carveout locations")
> Signed-off-by: Beleswar Padhi <b-padhi@...com>
> ---
> arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> index ffef3d1cfd55..9882bb1e8097 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts
> @@ -120,7 +120,8 @@ main_r5fss1_core1_memory_region: r5f-memory@...00000 {
> no-map;
> };
>
> - c66_0_dma_memory_region: c66-dma-memory@...00000 {
> + /* Carveout locations are flipped due to caching */
> + c66_1_dma_memory_region: c66-dma-memory@...00000 {
> compatible = "shared-dma-pool";
> reg = <0x00 0xa6000000 0x00 0x100000>;
> no-map;
> @@ -132,7 +133,8 @@ c66_0_memory_region: c66-memory@...00000 {
> no-map;
> };
>
> - c66_1_dma_memory_region: c66-dma-memory@...00000 {
> + /* Carveout locations are flipped due to caching */
> + c66_0_dma_memory_region: c66-dma-memory@...00000 {
> compatible = "shared-dma-pool";
> reg = <0x00 0xa7000000 0x00 0x100000>;
> no-map;
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