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Message-ID: <aJ6BHNcf2e9x8QmF@x1>
Date: Thu, 14 Aug 2025 17:36:44 -0700
From: Drew Fustini <fustini@...nel.org>
To: Icenowy Zheng <uwu@...nowy.me>
Cc: Guo Ren <guoren@...nel.org>, Fu Wei <wefu@...hat.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Michal Wilczynski <m.wilczynski@...sung.com>,
Yao Zi <ziyao@...root.org>, Han Gao <rabenda.cn@...il.com>,
linux-riscv@...ts.infradead.org, linux-clk@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 3/3] clk: thead: th1520-ap: set all AXI clocks to
CLK_IS_CRITICAL
On Wed, Aug 13, 2025 at 03:27:02PM +0800, Icenowy Zheng wrote:
> The AXI crossbar of TH1520 has no proper timeout handling, which means
> gating AXI clocks can easily lead to bus timeout and thus system hang.
>
> Set all AXI clock gates to CLK_IS_CRITICAL. All these clock gates are
> ungated by default on system reset.
>
> In addition, convert all current CLK_IGNORE_UNUSED usage to
> CLK_IS_CRITICAL to prevent unwanted clock gating.
>
> Signed-off-by: Icenowy Zheng <uwu@...nowy.me>
> ---
> No changes in v2 except for rebasing error fixes (which I sent as FIXED
> patches in v1).
>
> drivers/clk/thead/clk-th1520-ap.c | 44 +++++++++++++++----------------
> 1 file changed, 22 insertions(+), 22 deletions(-)
Reviewed-by: Drew Fustini <fustini@...nel.org>
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