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Message-Id: <20250816073234.77646-1-fangyu.yu@linux.alibaba.com>
Date: Sat, 16 Aug 2025 15:32:34 +0800
From: fangyu.yu@...ux.alibaba.com
To: anup@...infault.org,
atish.patra@...ux.dev,
paul.walmsley@...ive.com,
palmer@...belt.com,
aou@...s.berkeley.edu,
alex@...ti.fr
Cc: guoren@...ux.alibaba.com,
guoren@...nel.org,
kvm@...r.kernel.org,
kvm-riscv@...ts.infradead.org,
linux-riscv@...ts.infradead.org,
linux-kernel@...r.kernel.org,
Fangyu Yu <fangyu.yu@...ux.alibaba.com>
Subject: [PATCH] RISC-V: KVM: Write hgatp register with valid mode bits
From: Fangyu Yu <fangyu.yu@...ux.alibaba.com>
According to the RISC-V Privileged Architecture Spec, when MODE=Bare
is selected,software must write zero to the remaining fields of hgatp.
We have detected the valid mode supported by the HW before, So using a
valid mode to detect how many vmid bits are supported.
Signed-off-by: Fangyu Yu <fangyu.yu@...ux.alibaba.com>
---
arch/riscv/kvm/vmid.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/kvm/vmid.c b/arch/riscv/kvm/vmid.c
index 3b426c800480..d176a5c2f9a4 100644
--- a/arch/riscv/kvm/vmid.c
+++ b/arch/riscv/kvm/vmid.c
@@ -28,7 +28,7 @@ void __init kvm_riscv_gstage_vmid_detect(void)
/* Figure-out number of VMID bits in HW */
old = csr_read(CSR_HGATP);
- csr_write(CSR_HGATP, old | HGATP_VMID);
+ csr_write(CSR_HGATP, (kvm_riscv_gstage_mode() << HGATP_MODE_SHIFT) | HGATP_VMID);
vmid_bits = csr_read(CSR_HGATP);
vmid_bits = (vmid_bits & HGATP_VMID) >> HGATP_VMID_SHIFT;
vmid_bits = fls_long(vmid_bits);
--
2.49.0
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