linux-kernel - [PATCH v3 0/4] clk: thead: Changes to TH1520 clock driver for disp

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Message-ID: <20250816091113.2596048-1-uwu@icenowy.me>
Date: Sat, 16 Aug 2025 17:11:09 +0800
From: Icenowy Zheng <uwu@...nowy.me>
To: Drew Fustini <fustini@...nel.org>,
	Guo Ren <guoren@...nel.org>,
	Fu Wei <wefu@...hat.com>,
	Michael Turquette <mturquette@...libre.com>,
	Stephen Boyd <sboyd@...nel.org>,
	Michal Wilczynski <m.wilczynski@...sung.com>
Cc: Han Gao <rabenda.cn@...il.com>,
	Yao Zi <ziyao@...root.org>,
	linux-riscv@...ts.infradead.org,
	linux-clk@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Icenowy Zheng <uwu@...nowy.me>
Subject: [PATCH v3 0/4] clk: thead: Changes to TH1520 clock driver for disp

This patchset is my changes to the TH1520 clock driver, mainly for
supporting the display controller.

The first patch is previously a dependency of this patchset before v3,
but a rebase operation in v3 changed it and it's now pulled into this
patchset.

The 2nd and 3rd ones are functionality additions, with the first one
adding support for enabling/disabling PLLs (for DPU PLL) and the second
one adding support for changing DPU dividers.

The 4th one is to address hang issues met when testing the DPU driver
w/o clk_ignore_unused command line option.

The patchset is rebased atop the padctrl0 parent fix patchset (which
contains refactor of ccu_gate) at [1] in v3.

[1] https://lore.kernel.org/linux-riscv/20250816084445.2582692-1-uwu@icenowy.me/

Icenowy Zheng (3):
  clk: thead: add support for enabling/disabling PLLs
  clk: thead: support changing DPU pixel clock rate
  clk: thead: th1520-ap: set all AXI clocks to CLK_IS_CRITICAL

Michal Wilczynski (1):
  clk: thead: Correct parent for DPU pixel clocks

 drivers/clk/thead/clk-th1520-ap.c | 153 +++++++++++++++++++++++-------
 1 file changed, 121 insertions(+), 32 deletions(-)

-- 
2.50.1