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Message-ID: <953620e7-8873-481d-b235-8cbefcb08172@163.com>
Date: Sun, 17 Aug 2025 00:05:17 +0800
From: Hans Zhang <18255117159@....com>
To: bhelgaas@...gle.com, lpieralisi@...nel.org, kw@...ux.com,
krzk+dt@...nel.org, manivannan.sadhasivam@...aro.org, conor+dt@...nel.org
Cc: robh@...nel.org, linux-pci@...r.kernel.org, linux-kernel@...r.kernel.org,
devicetree@...r.kernel.org
Subject: Re: [PATCH v2 3/3] PCI: of: Relax max-link-speed check to support
PCIe Gen5/Gen6
Dear Bjorn,
Gentle ping.
Best regards,
Hans
On 2025/5/29 10:10, Hans Zhang wrote:
> The existing code restricted `max-link-speed` to values 1~4 (Gen1~Gen4),
> but current SOCs using Synopsys/Cadence IP may require Gen5/Gen6 support.
> This patch updates the validation in `of_pci_get_max_link_speed` to allow
> values up to 6, ensuring compatibility with newer PCIe generations.
>
> Signed-off-by: Hans Zhang <18255117159@....com>
> ---
> drivers/pci/of.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/pci/of.c b/drivers/pci/of.c
> index ab7a8252bf41..379d90913937 100644
> --- a/drivers/pci/of.c
> +++ b/drivers/pci/of.c
> @@ -890,7 +890,7 @@ int of_pci_get_max_link_speed(struct device_node *node)
> u32 max_link_speed;
>
> if (of_property_read_u32(node, "max-link-speed", &max_link_speed) ||
> - max_link_speed == 0 || max_link_speed > 4)
> + max_link_speed == 0 || max_link_speed > 6)
> return -EINVAL;
>
> return max_link_speed;
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