linux-kernel - [PATCH RFC net-next 10/23] net: dsa: lantiq_gswip: support enable/disable learning

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Message-ID: <aKDhl5LHSmwms9-h@pidgin.makrotopia.org>
Date: Sat, 16 Aug 2025 20:52:55 +0100
From: Daniel Golle <daniel@...rotopia.org>
To: Andrew Lunn <andrew@...n.ch>, Vladimir Oltean <olteanv@...il.com>,
	"David S. Miller" <davem@...emloft.net>,
	Eric Dumazet <edumazet@...gle.com>,
	Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>,
	Hauke Mehrtens <hauke@...ke-m.de>, Simon Horman <horms@...nel.org>,
	Russell King <linux@...linux.org.uk>,
	Florian Fainelli <f.fainelli@...il.com>,
	Arkadi Sharshevsky <arkadis@...lanox.com>,
	linux-kernel@...r.kernel.org, netdev@...r.kernel.org
Cc: Andreas Schirm <andreas.schirm@...mens.com>,
	Lukas Stockmann <lukas.stockmann@...mens.com>,
	Alexander Sverdlin <alexander.sverdlin@...mens.com>,
	Peter Christen <peter.christen@...mens.com>,
	Avinash Jayaraman <ajayaraman@...linear.com>,
	Bing tao Xu <bxu@...linear.com>, Liang Xu <lxu@...linear.com>,
	Juraj Povazanec <jpovazanec@...linear.com>,
	"Fanni (Fang-Yi) Chan" <fchan@...linear.com>,
	"Benny (Ying-Tsan) Weng" <yweng@...linear.com>,
	"Livia M. Rosu" <lrosu@...linear.com>,
	John Crispin <john@...ozen.org>
Subject: [PATCH RFC net-next 10/23] net: dsa: lantiq_gswip: support
 enable/disable learning

Switch API 2.3 or later supports enabling or disabling learning on each
port. Add basic support for that feature and use assisted learning on the
CPU port while enabling learning on user ports.

Signed-off-by: Daniel Golle <daniel@...rotopia.org>
---
 drivers/net/dsa/lantiq_gswip.c | 24 ++++++++++++++++++++++++
 drivers/net/dsa/lantiq_gswip.h |  3 +++
 2 files changed, 27 insertions(+)

diff --git a/drivers/net/dsa/lantiq_gswip.c b/drivers/net/dsa/lantiq_gswip.c
index 16b92af9ff23..fde31c5bd8ae 100644
--- a/drivers/net/dsa/lantiq_gswip.c
+++ b/drivers/net/dsa/lantiq_gswip.c
@@ -448,6 +448,18 @@ static int gswip_add_single_port_br(struct gswip_priv *priv, int port, bool add)
 	return 0;
 }
 
+static void gswip_port_set_learning(struct gswip_priv *priv, int port,
+				    bool enable)
+{
+	if (!GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_3))
+		return;
+
+	/* learning disable bit */
+	gswip_switch_mask(priv, GSWIP_PCE_PCTRL_3_LNDIS,
+			  enable ? 0 : GSWIP_PCE_PCTRL_3_LNDIS,
+			  GSWIP_PCE_PCTRL_3p(port));
+}
+
 static int gswip_port_enable(struct dsa_switch *ds, int port,
 			     struct phy_device *phydev)
 {
@@ -592,10 +604,19 @@ static int gswip_setup(struct dsa_switch *ds)
 	}
 
 	/* Default unknown Broadcast/Multicast/Unicast port maps */
+	/* Monitoring Port Map */
 	gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP1);
+	/* Default unknown Broadcast/Multicast Port Map */
 	gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP2);
+	/* Default unknown Unicast Port Map */
 	gswip_switch_w(priv, cpu_ports, GSWIP_PCE_PMAP3);
 
+	/* enable MAC address learning by default on all user ports, disable
+	 * on the CPU port to use assisted learning on the CPU port
+	 */
+	for (i = 0; i < priv->hw_info->max_ports; i++)
+		gswip_port_set_learning(priv, i, !dsa_is_cpu_port(ds, i));
+
 	/* Deactivate MDIO PHY auto polling. Some PHYs as the AR8030 have an
 	 * interoperability problem with this auto polling mechanism because
 	 * their status registers think that the link is in a different state
@@ -653,6 +674,9 @@ static int gswip_setup(struct dsa_switch *ds)
 
 	ds->configure_vlan_while_not_filtering = false;
 
+	if (GSWIP_VERSION_GE(priv, GSWIP_VERSION_2_3))
+		ds->assisted_learning_on_cpu_port = true;
+
 	return 0;
 }
 
diff --git a/drivers/net/dsa/lantiq_gswip.h b/drivers/net/dsa/lantiq_gswip.h
index fd0c01edb914..b565ebebbc46 100644
--- a/drivers/net/dsa/lantiq_gswip.h
+++ b/drivers/net/dsa/lantiq_gswip.h
@@ -151,6 +151,9 @@
 #define  GSWIP_PCE_PCTRL_0_PSTATE_LEARNING	0x3
 #define  GSWIP_PCE_PCTRL_0_PSTATE_FORWARDING	0x7
 #define  GSWIP_PCE_PCTRL_0_PSTATE_MASK	GENMASK(2, 0)
+/* Ethernet Switch PCE Port Control Register 3 */
+#define GSWIP_PCE_PCTRL_3p(p)		(0x483 + ((p) * 0xA))
+#define  GSWIP_PCE_PCTRL_3_LNDIS	BIT(15)  /* Learning Disable */
 #define GSWIP_PCE_VCTRL(p)		(0x485 + ((p) * 0xA))
 #define  GSWIP_PCE_VCTRL_UVR		BIT(0)	/* Unknown VLAN Rule */
 #define  GSWIP_PCE_VCTRL_VIMR		BIT(3)	/* VLAN Ingress Member violation rule */
-- 
2.50.1