linux-kernel - RE: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values

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Message-ID:
 <TY3PR01MB113461793362E7286253037468636A@TY3PR01MB11346.jpnprd01.prod.outlook.com>
Date: Sun, 17 Aug 2025 12:06:06 +0000
From: Biju Das <biju.das.jz@...renesas.com>
To: biju.das.au <biju.das.au@...il.com>, Geert Uytterhoeven
	<geert+renesas@...der.be>, Linus Walleij <linus.walleij@...aro.org>
CC: Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>,
	"linux-renesas-soc@...r.kernel.org" <linux-renesas-soc@...r.kernel.org>,
	"linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
	"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>, biju.das.au
	<biju.das.au@...il.com>
Subject: RE: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if
 it is same as reset values

Hi All,

> -----Original Message-----
> From: Biju <biju.das.au@...il.com>
> Sent: 15 August 2025 15:48
> Subject: [PATCH 2/2] pinctrl: renesas: rzg2l: Don't reconfigure the pin if it is same as reset values
> 
> From: Biju Das <biju.das.jz@...renesas.com>
> 
> Don't reconfigure the pin if the pin's configuration values are same as reset values during resume() to
> avoid spurious IRQ. E.g: For NMI function the PS0 pin configuration are PMC = 1 and PFC = 0 and is same
> as that of reset values. Currently during resume the pin is already in NMI function.
> But the code is forcefully setting it to GPIO HI-Z state and then again reconfiguring to NMI function
> leading to spurious IRQ.
> 
> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
> ---
>  drivers/pinctrl/renesas/pinctrl-rzg2l.c | 34 +++++++++++++++----------
>  1 file changed, 21 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 2b5d16594bb7..086fcb18c6d8 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -3103,27 +3103,35 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
>  		pm = readw(pctrl->base + PM(off));
>  		for_each_set_bit(pin, &pinmap, max_pin) {
>  			struct rzg2l_pinctrl_reg_cache *cache = pctrl->cache;
> +			u32 pfc_mask;
> +			u32 pfc_val;
> 
>  			/* Nothing to do if PFC was not configured before. */
>  			if (!(cache->pmc[port] & BIT(pin)))
>  				continue;
> 
> -			/* Set pin to 'Non-use (Hi-Z input protection)' */
> -			pm &= ~(PM_MASK << (pin * 2));
> -			writew(pm, pctrl->base + PM(off));
> +			pfc_val = readl(pctrl->base + PFC(off));
> +			pfc_mask = PFC_MASK << (pin * 4);
> 
> -			/* Temporarily switch to GPIO mode with PMC register */
> -			pmc &= ~BIT(pin);
> -			writeb(pmc, pctrl->base + PMC(off));
> +			/* Nothing to do if reset value of the pin is same as cached value */
> +			if ((cache->pfc[port] & pfc_mask) != (pfc_val & pfc_mask)) {
> +				/* Set pin to 'Non-use (Hi-Z input protection)' */
> +				pm &= ~(PM_MASK << (pin * 2));
> +				writew(pm, pctrl->base + PM(off));
> 
> -			/* Select Pin function mode. */
> -			pfc &= ~(PFC_MASK << (pin * 4));
> -			pfc |= (cache->pfc[port] & (PFC_MASK << (pin * 4)));
> -			writel(pfc, pctrl->base + PFC(off));
> +				/* Temporarily switch to GPIO mode with PMC register */
> +				pmc &= ~BIT(pin);
> +				writeb(pmc, pctrl->base + PMC(off));
> 
> -			/* Switch to Peripheral pin function. */
> -			pmc |= BIT(pin);
> -			writeb(pmc, pctrl->base + PMC(off));
> +				/* Select Pin function mode. */
> +				pfc &= ~pfc_mask;
> +				pfc |= cache->pfc[port] & pfc_mask;
> +				writel(pfc, pctrl->base + PFC(off));
> +
> +				/* Switch to Peripheral pin function. */
> +				pmc |= BIT(pin);
> +				writeb(pmc, pctrl->base + PMC(off));
> +			}

I will send v2, as I forgot to update rzg2l_pinctrl_set_pfc_mode()
Aswell.

Cheers,
Biju



>  		}
>  	}
> 
> --
> 2.43.0