linux-kernel - Re: [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to limit frequency

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Message-ID: <CALHNRZ9kLabyFv5PiMb7jrZgPyjOKe5sWEq7EJPb5LO6E6FUMg@mail.gmail.com>
Date: Sun, 17 Aug 2025 22:23:10 -0500
From: Aaron Kling <webgeek1234@...il.com>
To: Krzysztof Kozlowski <krzk@...nel.org>
Cc: Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Rob Herring <robh@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Conor Dooley <conor+dt@...nel.org>, 
	Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, 
	Joseph Lo <josephl@...dia.com>, Peter De Schrijver <pdeschrijver@...dia.com>, 
	Prashant Gaikwad <pgaikwad@...dia.com>, linux-clk@...r.kernel.org, devicetree@...r.kernel.org, 
	linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org, 
	Thierry Reding <treding@...dia.com>
Subject: Re: [PATCH 1/5] dt-bindings: clock: tegra124-dfll: Add property to
 limit frequency

On Sat, Aug 16, 2025 at 3:21 AM Krzysztof Kozlowski <krzk@...nel.org> wrote:
>
> On 16/08/2025 07:53, Aaron Kling via B4 Relay wrote:
> > From: Aaron Kling <webgeek1234@...il.com>
> >
> > Some devices report a cpu speedo value that corresponds to a table that
> > scales beyond the chips capability. This allows devices to set a lower
> > limit.
> >
> > Signed-off-by: Aaron Kling <webgeek1234@...il.com>
> > ---
> >  Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt | 3 +++
> >  1 file changed, 3 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > index f7d347385b5775ddd702ecbb9821acfc9d4b9ff2..6cdbabc1f036a767bdc8e5df64eeff34171a3b85 100644
> > --- a/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > +++ b/Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
> > @@ -70,6 +70,9 @@ Required properties for PWM mode:
> >    - dvfs_pwm_enable: I/O pad configuration when PWM control is enabled.
> >    - dvfs_pwm_disable: I/O pad configuration when PWM control is disabled.
> >
> > +Optional properties for limiting frequency:
> > +- nvidia,dfll-max-freq: Maximum scaling frequency.
>
>
> 1. Frequency is in units.
Ack, will fix in whatever form a new revision takes.

> 2. OPP defines it already, doesn't it?
The dfll driver generates the cpu opp table based on soc sku's, it
doesn't use dt opp tables. This property is intended to modify the
generation of said table. That said, if there's a generic dt opp
paradigm for this that I missed which works without dt opp tables, I'd
be happy to use that instead.

> 3. You need to convert file to DT schema first. No new properties are
> allowed in text.
Per an attempt to auto-convert this binding [0], there's a pending
copy already. As I don't want to duplicate existing work, I'll have to
wait on that then.

Aaron

[0] https://lore.kernel.org/all/20250630232632.3700405-1-robh@kernel.org/