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Message-ID: <20250818163933.62086-3-matthew.gerlach@altera.com>
Date: Mon, 18 Aug 2025 09:39:33 -0700
From: Matthew Gerlach <matthew.gerlach@...era.com>
To: dinguyen@...nel.org,
robh@...nel.org,
krzk+dt@...nel.org,
conor+dt@...nel.org,
richardcochran@...il.com,
devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Matthew Gerlach <matthew.gerlach@...era.com>
Subject: [PATCH v3 2/2] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected
to a RGMII PHY on a daughter card. There are no RGMII clock delays
implemented the on PCB.
Signed-off-by: Matthew Gerlach <matthew.gerlach@...era.com>
---
v3:
- No change from v2.
v2:
- change phy-mode to "rgmii-id"
- add newline before inner device tree nodes
---
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..e9776e1cdc9a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -10,6 +10,9 @@ / {
aliases {
serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
};
chosen {
@@ -37,6 +40,23 @@ &gpio0 {
status = "okay";
};
+&gmac2 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ phy-handle = <&emac2_phy0>;
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+
+ emac2_phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+ };
+};
+
&gpio1 {
status = "okay";
};
--
2.35.3
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