[<prev] [next>] [day] [month] [year] [list]
Message-ID: <3542795.LZWGnKmheA@n9w6sw14>
Date: Mon, 18 Aug 2025 19:02:49 +0200
From: Christian Eggers <ceggers@...i.de>
To: Miquel Raynal <miquel.raynal@...tlin.com>, Richard Weinberger
<richard@....at>, <linux-mtd@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>
Subject: mtd: rawnand: Inconsistent parameter page on Foresee FSNS8A002G ?
I try to use a Foresee FSNS8A002G SLC flash chip on an i.MX6 GPMI controller:
https://www.lcsc.com/datasheet/C5126835.pdf
The kernel output looks promising, but one line looks suspicious:
...
nand: device found, Manufacturer ID: 0xcd, Chip ID: 0xda
nand: Foresee FSNS8A002G
nand: 256 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64
nand: SDR timing mode 4 not acknowledged by the NAND chip
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Bad block table found at page 131008, version 0x01
Bad block table found at page 130944, version 0x01
3 fixed-partitions partitions found on MTD device gpmi-nand
...
According to the documentation of "Read Parameter Page", byte 129-130,
SDR modes 0 to 5 should be supported (page 19 on the data sheet).
But the documentation of the GET_FEATURE/SET_FEATURE operation misses
the "Timing mode" register (data sheet, page 24).
I saw that there is a quirk for some Macronix chips which also seem
not to support getting/setting the timing mode (but declaring them
in the parameter page).
My main question is whether this is "normal variation within the flash
market" or a serious issue. In contrast to another device I currently
use, the Foresee chip also doesn't support "cached" operations. Is there
much value writing a fix for Timing Mode issue, or should I better
use another flash device?
regards,
Christian
Powered by blists - more mailing lists