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Message-ID: <ac9769af-9ab6-4b48-9890-ec3bcda3b180@kernel.org>
Date: Mon, 18 Aug 2025 10:24:17 +0200
From: Krzysztof Kozlowski <krzk@...nel.org>
To: Inbaraj E <inbaraj.e@...sung.com>, mturquette@...libre.com,
sboyd@...nel.org, robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
s.nawrocki@...sung.com, s.hauer@...gutronix.de, shawnguo@...nel.org,
cw00.choi@...sung.com, rmfrfs@...il.com, laurent.pinchart@...asonboard.com,
martink@...teo.de, mchehab@...nel.org, linux-fsd@...la.com, will@...nel.org,
catalin.marinas@....com, pankaj.dubey@...sung.com, shradha.t@...sung.com,
ravi.patel@...sung.com
Cc: linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, alim.akhtar@...sung.com,
linux-samsung-soc@...r.kernel.org, kernel@...i.sm, kernel@...gutronix.de,
festevam@...il.com, linux-media@...r.kernel.org, imx@...ts.linux.dev,
linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 03/12] dt-bindings: media: nxp: Add support for FSD SoC
On 14/08/2025 16:09, Inbaraj E wrote:
> Document the MIPI CSI2 controller device tree bindings for Tesla
> FSD SoC
Explain the hardware.
>
> Signed-off-by: Inbaraj E <inbaraj.e@...sung.com>
> ---
> .../bindings/media/nxp,imx-mipi-csi2.yaml | 88 ++++++++++++++-----
> 1 file changed, 68 insertions(+), 20 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> index 03a23a26c4f3..802fb1bd150d 100644
> --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml
> @@ -14,7 +14,7 @@ description: |-
> The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
> receiver IP core named CSIS. The IP core originates from Samsung, and may be
> compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
> - 3.3, and i.MX8 SoCs use CSIS version 3.6.3.
> + 3.3, i.MX8 SoCs use CSIS version 3.6.3 and FSD SoC uses CSIS version 4.3.
>
> While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
> completely wrapped by the CSIS and doesn't expose a control interface of its
> @@ -26,6 +26,7 @@ properties:
> - enum:
> - fsl,imx7-mipi-csi2
> - fsl,imx8mm-mipi-csi2
> + - tesla,fsd-mipi-csi2
Isn't this Samsung CSI IP? Why are you adding it to NXP? Nothing in
commit msg helps me to understand that.
> - items:
> - enum:
> - fsl,imx8mp-mipi-csi2
> @@ -38,24 +39,21 @@ properties:
> maxItems: 1
>
> clocks:
> - minItems: 3
> - items:
> - - description: The peripheral clock (a.k.a. APB clock)
> - - description: The external clock (optionally used as the pixel clock)
> - - description: The MIPI D-PHY clock
> - - description: The AXI clock
> + minItems: 2
> + maxItems: 4
>
> clock-names:
> - minItems: 3
> - items:
> - - const: pclk
> - - const: wrap
> - - const: phy
> - - const: axi
> + minItems: 2
> + maxItems: 4
>
> power-domains:
> maxItems: 1
>
> + samsung,syscon-csis:
samsung, so not nxp. Even more confusing.
Best regards,
Krzysztof
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