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Message-Id: <DC5HEJRMZ84K.34OPU922A7XBE@ventanamicro.com>
Date: Mon, 18 Aug 2025 12:29:10 +0200
From: Radim Krčmář <rkrcmar@...tanamicro.com>
To: "Anup Patel" <apatel@...tanamicro.com>, "Atish Patra"
<atish.patra@...ux.dev>
Cc: "Palmer Dabbelt" <palmer@...belt.com>, "Paul Walmsley"
<paul.walmsley@...ive.com>, "Alexandre Ghiti" <alex@...ti.fr>, "Andrew
Jones" <ajones@...tanamicro.com>, "Anup Patel" <anup@...infault.org>,
"Paolo Bonzini" <pbonzini@...hat.com>, "Shuah Khan" <shuah@...nel.org>,
<kvm@...r.kernel.org>, <kvm-riscv@...ts.infradead.org>,
<linux-riscv@...ts.infradead.org>, <linux-kernel@...r.kernel.org>,
<linux-kselftest@...r.kernel.org>, "linux-riscv"
<linux-riscv-bounces@...ts.infradead.org>
Subject: Re: [PATCH 0/6] ONE_REG interface for SBI FWFT extension
2025-08-14T21:25:42+05:30, Anup Patel <apatel@...tanamicro.com>:
> This series adds ONE_REG interface for SBI FWFT extension implemented
> by KVM RISC-V.
I think it would be better to ONE_REG the CSRs (medeleg/menvcfg), or at
least expose their CSR fields (each sensible medeleg bit, PMM, ...)
through kvm_riscv_config, than to couple this with SBI/FWFT.
The controlled behavior is defined by the ISA, and userspace might want
to configure the S-mode execution environment even when SBI/FWFT is not
present, which is not possible with the current design.
Is there a benefit in expressing the ISA model through SBI/FWFT?
Thanks.
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