linux-kernel - [PATCH v2 0/3] ESWIN EIC7700 sata phy driver and yaml,

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Message-Id: <20250819134722.220-1-luyulin@eswincomputing.com>
Date: Tue, 19 Aug 2025 21:47:22 +0800
From: Yulin Lu <luyulin@...incomputing.com>
To: dlemoal@...nel.org,
	cassel@...nel.org,
	robh@...nel.org,
	krzk+dt@...nel.org,
	conor+dt@...nel.org,
	linux-ide@...r.kernel.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	vkoul@...nel.org,
	kishon@...nel.org,
	linux-phy@...ts.infradead.org
Cc: ningyu@...incomputing.com,
	zhengyu@...incomputing.com,
	linmin@...incomputing.com,
	huangyifeng@...incomputing.com,
	fenglin@...incomputing.com,
	lianghujun@...incomputing.com,
	luyulin <luyulin@...incomputing.com>
Subject: [PATCH v2 0/3] ESWIN EIC7700 sata phy driver and yaml,

From: luyulin <luyulin@...incomputing.com>

  Implements support for the Eswin EIC7700 SoC sata phy.
  Implements the calling sequence to interface with dwc-ahci,
  ensuring correct hardware execution order.
  Integration with the Linux phy subsystem for consistency and
  scalability.
  Add documentation for ahci and sata phy on the ESWIN EIC7700
  SoC platform.

  Supported chips:
    Eswin EIC7700 SoC.

  Test:
    Tested this patch on the Sifive HiFive Premier P550 (which uses
    the EIC7700 SoC). Based on this driver, the SATA device read/write
    operations are functioning normally, supporting SATA 1.5 Gb/s,
    3.0 Gb/s, and 6.0 Gb/s speeds, so this verifies that this sata
    driver patch is working properly.

  This series depends on the vendor prefix patch [1] and config option patch [2].
  [1] https://lore.kernel.org/all/20250616112316.3833343-4-pinkesh.vaghela@einfochips.com/
  [2] https://lore.kernel.org/all/20250616112316.3833343-3-pinkesh.vaghela@einfochips.com/

Updates:

  Changes since V1:
    - Delete the original controller driver and use ahci_dwc.c instead.
    - Add eswin,eic7700-ahci.yaml
      - Correct the descriptions of reset, interrupt and other
        hardware resources for the sata controller on EIC7700 SoC.
      - The clocks for both sata controller and sata PHY are controlled
        via a register bit in the HSP bus and are not registered in the
        clock tree. Clock are managed within the PHY driver, therefore
        it is not described in this document.
      - Add $ref: snps,dwc-ahci-common.yaml#.
    - Add eswin,eic7700-sata-phy.yaml
      - Add this file to include the description of the PHY on EIC7700 SoC.
    - Add an eswin directory under the PHY driver path, and include the SATA
      PHY driver code for EIC7700 SoC.
    - Link to v1: https://lore.kernel.org/all/20250515085114.1692-1-hehuan1@eswincomputing.com/

luyulin (3):
  dt-bindings: ata: eswin: Document for EIC7700 SoC ahci
  dt-bindings: phy: eswin: Document for EIC7700 SoC SATA
  phy: eswin: Create eswin directory and add EIC7700 SATA PHY driver

 .../bindings/ata/eswin,eic7700-ahci.yaml      |  92 ++++++++
 .../bindings/phy/eswin,eic7700-sata-phy.yaml  |  36 ++++
 drivers/phy/Kconfig                           |   1 +
 drivers/phy/Makefile                          |   1 +
 drivers/phy/eswin/Kconfig                     |  14 ++
 drivers/phy/eswin/Makefile                    |   2 +
 drivers/phy/eswin/phy-eic7700-sata.c          | 197 ++++++++++++++++++
 7 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ata/eswin,eic7700-ahci.yaml
 create mode 100644 Documentation/devicetree/bindings/phy/eswin,eic7700-sata-phy.yaml
 create mode 100644 drivers/phy/eswin/Kconfig
 create mode 100644 drivers/phy/eswin/Makefile
 create mode 100644 drivers/phy/eswin/phy-eic7700-sata.c

-- 
2.25.1