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Message-ID: <ef115fd1-01e9-4d36-9c6d-37ea7516123c@oracle.com>
Date: Tue, 19 Aug 2025 23:06:11 +0530
From: ALOK TIWARI <alok.a.tiwari@...cle.com>
To: hans.zhang@...tech.com, bhelgaas@...gle.com, lpieralisi@...nel.org,
kw@...ux.com, mani@...nel.org, robh@...nel.org, kwilczynski@...nel.org,
krzk+dt@...nel.org, conor+dt@...nel.org
Cc: mpillai@...ence.com, fugang.duan@...tech.com, guoyin.chen@...tech.com,
peter.chen@...tech.com, cix-kernel-upstream@...tech.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v8 03/15] PCI: cadence: Add register definitions for High
Perf Architecture (HPA)
On 8/19/2025 5:22 PM, hans.zhang@...tech.com wrote:
> +#define HPA_LM_RC_BAR_CFG_CTRL_DISABLED(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_DISABLED << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_IO_32BITS(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_IO_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_32BITS(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_32BITS(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_MEM_64BITS(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_MEM_64BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_CTRL_PREF_MEM_64BITS(bar) \
> + (CDNS_PCIE_HPA_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS << ((bar) * 10))
> +#define HPA_LM_RC_BAR_CFG_APERTURE(bar, aperture) \
> + (((aperture) - 7) << ((bar) * 10))
> +
> +#define CDNS_PCIE_HPA_LM_PTM_CTRL 0x0520
> +#define CDNS_PCIE_HPA_LM_TPM_CTRL_PTMRSEN BIT(17)
Is that TPM intentional or a typo?
Thanks,
Alok
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