linux-kernel - Re: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR

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Message-ID: <CAC=S1njekmPyq5653Ybi8+7i2_+Dx978aJOQNUTuRBs0ef0sfw@mail.gmail.com>
Date: Tue, 19 Aug 2025 14:01:29 +0800
From: Fei Shao <fshao@...omium.org>
To: "payne.lin" <payne.lin@...iatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>, Philipp Zabel <p.zabel@...gutronix.de>, 
	David Airlie <airlied@...il.com>, Simona Vetter <simona@...ll.ch>, 
	Matthias Brugger <matthias.bgg@...il.com>, 
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>, dri-devel@...ts.freedesktop.org, 
	linux-mediatek@...ts.infradead.org, linux-kernel@...r.kernel.org, 
	linux-arm-kernel@...ts.infradead.org, 
	Project_Global_Chrome_Upstream_Group@...iatek.com, sirius.wang@...iatek.com, 
	vince-wl.liu@...iatek.com, jh.hsu@...iatek.com, 
	Bincai Liu <bincai.liu@...iatek.com>
Subject: Re: [PATCH] gpu: drm: mediatek: correct clk setting AUX_RX_UI_CNT_THR_AUX_FOR_26M

On Mon, Aug 18, 2025 at 9:37 PM payne.lin <payne.lin@...iatek.com> wrote:
>

Start the patch title with "drm/mediatek: ".

> From: Bincai Liu <bincai.liu@...iatek.com>
>
> Updated the definition of AUX_RX_UI_CNT_THR_AUX_FOR_26M from 13 to 14.
> No other code or logic changes were made; only the macro value was modified.
> This change affects the timing configuration for AUX RX at 26MHz.
> The formula is xtal_clk / 2 + 1.

The datasheet says "It should be set to the ratio of the half cycle
XTAL clock to the 1MHz clock.", which doesn't align with your formula,
so please explain (1) why this is needed and (2) whether it's tested
on any MT8195 or MT8188 based devices, in the commit message.

Also, you'll need a "Fixes:" tag[1] if this fixes a bug.

Regards,
Fei

[1]: https://www.kernel.org/doc/html/latest/process/submitting-patches.html#describe-your-changes


>
> Signed-off-by: Bincai Liu <bincai.liu@...iatek.com>
> Signed-off-by: Payne Lin <payne.lin@...iatek.com>
> ---
>  drivers/gpu/drm/mediatek/mtk_dp_reg.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_dp_reg.h b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> index 8ad7a9cc259e..f8c7b3c0935f 100644
> --- a/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> +++ b/drivers/gpu/drm/mediatek/mtk_dp_reg.h
> @@ -301,7 +301,7 @@
>  #define AUX_TIMEOUT_THR_AUX_TX_P0_VAL                  0x1595
>  #define MTK_DP_AUX_P0_3614                     0x3614
>  #define AUX_RX_UI_CNT_THR_AUX_TX_P0_MASK               GENMASK(6, 0)
> -#define AUX_RX_UI_CNT_THR_AUX_FOR_26M                  13
> +#define AUX_RX_UI_CNT_THR_AUX_FOR_26M                  14
>  #define MTK_DP_AUX_P0_3618                     0x3618
>  #define AUX_RX_FIFO_FULL_AUX_TX_P0_MASK                        BIT(9)
>  #define AUX_RX_FIFO_WRITE_POINTER_AUX_TX_P0_MASK       GENMASK(3, 0)
> --
> 2.45.2
>
>