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Message-ID: <06bcf2f6-4a3e-4f87-93e4-29e17ae89e62@quicinc.com>
Date: Wed, 20 Aug 2025 18:18:52 +0530
From: Jyothi Kumar Seerapu <quic_jseerapu@...cinc.com>
To: Mikhail Kshevetskiy <mikhail.kshevetskiy@...sys.eu>,
Lorenzo Bianconi
<lorenzo@...nel.org>, Ray Liu <ray.liu@...oha.com>,
Mark Brown
<broonie@...nel.org>,
<linux-arm-kernel@...ts.infradead.org>, <linux-spi@...r.kernel.org>,
<linux-kernel@...r.kernel.org>,
Frieder Schrempf
<frieder.schrempf@...tron.de>
Subject: Re: [PATCH v3 03/14] spi: airoha: add support of dual/quad wires spi
modes
On 8/20/2025 6:03 PM, Mikhail Kshevetskiy wrote:
> This patch adds support of dual and quad wires spi modes. It will
> speed up flash operations on the hardware with corresponding hardware
> support.
>
> Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@...sys.eu>
> ---
> drivers/spi/spi-airoha-snfi.c | 107 +++++++++++++++++++++++++---------
> 1 file changed, 80 insertions(+), 27 deletions(-)
>
> diff --git a/drivers/spi/spi-airoha-snfi.c b/drivers/spi/spi-airoha-snfi.c
> index bcc464ec9c61..7aab3506834a 100644
> --- a/drivers/spi/spi-airoha-snfi.c
> +++ b/drivers/spi/spi-airoha-snfi.c
> @@ -192,6 +192,14 @@
> #define SPI_NAND_OP_RESET 0xff
> #define SPI_NAND_OP_DIE_SELECT 0xc2
>
> +/* SNAND FIFO commands */
> +#define SNAND_FIFO_TX_BUSWIDTH_SINGLE 0x08
> +#define SNAND_FIFO_TX_BUSWIDTH_DUAL 0x09
> +#define SNAND_FIFO_TX_BUSWIDTH_QUAD 0x0a
> +#define SNAND_FIFO_RX_BUSWIDTH_SINGLE 0x0c
> +#define SNAND_FIFO_RX_BUSWIDTH_DUAL 0x0e
> +#define SNAND_FIFO_RX_BUSWIDTH_QUAD 0x0f
> +
> #define SPI_NAND_CACHE_SIZE (SZ_4K + SZ_256)
> #define SPI_MAX_TRANSFER_SIZE 511
>
> @@ -387,10 +395,25 @@ static int airoha_snand_set_mode(struct airoha_snand_ctrl *as_ctrl,
> return regmap_write(as_ctrl->regmap_ctrl, REG_SPI_CTRL_DUMMY, 0);
> }
>
> -static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
> - const u8 *data, int len)
> +static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl,
> + const u8 *data, int len, int buswidth)
> {
> int i, data_len;
> + u8 cmd;
> +
> + switch (buswidth) {
> + case 1:
> + cmd = SNAND_FIFO_TX_BUSWIDTH_SINGLE;
> + break;
> + case 2:
> + cmd = SNAND_FIFO_TX_BUSWIDTH_DUAL;
> + break;
> + case 4:
> + cmd = SNAND_FIFO_TX_BUSWIDTH_QUAD;
> + break;
> + default:
> + return -EINVAL;
> + }
>
> for (i = 0; i < len; i += data_len) {
> int err;
> @@ -409,16 +432,31 @@ static int airoha_snand_write_data(struct airoha_snand_ctrl *as_ctrl, u8 cmd,
> return 0;
> }
>
> -static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl, u8 *data,
> - int len)
> +static int airoha_snand_read_data(struct airoha_snand_ctrl *as_ctrl,
> + u8 *data, int len, int buswidth)
> {
> int i, data_len;
> + u8 cmd;
> +
> + switch (buswidth) {
> + case 1:
> + cmd = SNAND_FIFO_RX_BUSWIDTH_SINGLE;
> + break;
> + case 2:
> + cmd = SNAND_FIFO_RX_BUSWIDTH_DUAL;
> + break;
> + case 4:
> + cmd = SNAND_FIFO_RX_BUSWIDTH_QUAD;
> + break;
> + default:
> + return -EINVAL;
For unknown buswidth cases, not falling back to single lane?
What if the bus width is 0 ? (for SPI, typically default
SPI_NBITS_SINGLE is used for buswidth 0).> + }
>
> for (i = 0; i < len; i += data_len) {
> int err;
>
> data_len = min(len - i, SPI_MAX_TRANSFER_SIZE);
> - err = airoha_snand_set_fifo_op(as_ctrl, 0xc, data_len);
> + err = airoha_snand_set_fifo_op(as_ctrl, cmd, data_len);
> if (err)
> return err;
>
> @@ -895,12 +933,27 @@ static ssize_t airoha_snand_dirmap_write(struct spi_mem_dirmap_desc *desc,
> static int airoha_snand_exec_op(struct spi_mem *mem,
> const struct spi_mem_op *op)
> {
> - u8 data[8], cmd, opcode = op->cmd.opcode;
> struct airoha_snand_ctrl *as_ctrl;
> - int i, err;
> + char buf[20], *data;
> + int i, err, op_len, addr_len, dummy_len;
>
> as_ctrl = spi_controller_get_devdata(mem->spi->controller);
>
> + op_len = op->cmd.nbytes;
> + addr_len = op->addr.nbytes;
> + dummy_len = op->dummy.nbytes;
> +
> + if (op_len + dummy_len + addr_len > sizeof(buf))
> + return -EIO;
> +
> + data = buf;
> + for (i = 0; i < op_len; i++)
> + *data++ = op->cmd.opcode >> (8 * (op_len - i - 1));
> + for (i = 0; i < addr_len; i++)
> + *data++ = op->addr.val >> (8 * (addr_len - i - 1));
> + for (i = 0; i < dummy_len; i++)
> + *data++ = 0xff;
> +
> /* switch to manual mode */
> err = airoha_snand_set_mode(as_ctrl, SPI_MODE_MANUAL);
> if (err < 0)
> @@ -911,40 +964,40 @@ static int airoha_snand_exec_op(struct spi_mem *mem,
> return err;
>
> /* opcode */
> - err = airoha_snand_write_data(as_ctrl, 0x8, &opcode, sizeof(opcode));
> + data = buf;
> + err = airoha_snand_write_data(as_ctrl, data, op_len,
> + op->cmd.buswidth);
> if (err)
> return err;
>
> /* addr part */
> - cmd = opcode == SPI_NAND_OP_GET_FEATURE ? 0x11 : 0x8;
> - put_unaligned_be64(op->addr.val, data);
> -
> - for (i = ARRAY_SIZE(data) - op->addr.nbytes;
> - i < ARRAY_SIZE(data); i++) {
> - err = airoha_snand_write_data(as_ctrl, cmd, &data[i],
> - sizeof(data[0]));
> + data += op_len;
> + if (addr_len) {
> + err = airoha_snand_write_data(as_ctrl, data, addr_len,
> + op->addr.buswidth);
> if (err)
> return err;
> }
>
> /* dummy */
> - data[0] = 0xff;
> - for (i = 0; i < op->dummy.nbytes; i++) {
> - err = airoha_snand_write_data(as_ctrl, 0x8, &data[0],
> - sizeof(data[0]));
> + data += addr_len;
> + if (dummy_len) {
> + err = airoha_snand_write_data(as_ctrl, data, dummy_len,
> + op->dummy.buswidth);
> if (err)
> return err;
> }
>
> /* data */
> - if (op->data.dir == SPI_MEM_DATA_IN) {
> - err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
> - op->data.nbytes);
> - if (err)
> - return err;
> - } else {
> - err = airoha_snand_write_data(as_ctrl, 0x8, op->data.buf.out,
> - op->data.nbytes);
> + if (op->data.nbytes) {
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + err = airoha_snand_read_data(as_ctrl, op->data.buf.in,
> + op->data.nbytes,
> + op->data.buswidth);
> + else
> + err = airoha_snand_write_data(as_ctrl, op->data.buf.out,
> + op->data.nbytes,
> + op->data.buswidth);
> if (err)
> return err;
> }
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