linux-kernel - Re: [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps

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Message-ID: <aKX1CxD_2mlOwYn-@vaman>
Date: Wed, 20 Aug 2025 21:47:15 +0530
From: Vinod Koul <vkoul@...nel.org>
To: "payne.lin" <payne.lin@...iatek.com>
Cc: Chun-Kuang Hu <chunkuang.hu@...nel.org>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Chunfeng Yun <chunfeng.yun@...iatek.com>,
	Kishon Vijay Abraham I <kishon@...nel.org>,
	Matthias Brugger <matthias.bgg@...il.com>,
	AngeloGioacchino Del Regno <angelogioacchino.delregno@...labora.com>,
	dri-devel@...ts.freedesktop.org, linux-mediatek@...ts.infradead.org,
	linux-arm-kernel@...ts.infradead.org, linux-phy@...ts.infradead.org,
	linux-kernel@...r.kernel.org,
	Project_Global_Chrome_Upstream_Group@...iatek.com,
	sirius.wang@...iatek.com, vince-wl.liu@...iatek.com,
	jh.hsu@...iatek.com, Bincai Liu <bincai.liu@...iatek.com>
Subject: Re: [PATCH] phy: mediatek: Modify mipi clk upper bound to 2.5Gbps

On 14-08-25, 20:54, payne.lin wrote:
> From: Bincai Liu <bincai.liu@...iatek.com>
> 
> Mipi dphy can support up to 4k30 without dsc.

Good, how does that translate to below value change, can you please
explain?

> 
> Signed-off-by: Bincai Liu <bincai.liu@...iatek.com>
> Signed-off-by: Payne Lin <payne.lin@...iatek.com>
> ---
>  drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> index 553725e1269c..b8233c496070 100644
> --- a/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> +++ b/drivers/phy/mediatek/phy-mtk-mipi-dsi-mt8183.c
> @@ -100,7 +100,7 @@ static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
>  static long mtk_mipi_tx_pll_round_rate(struct clk_hw *hw, unsigned long rate,
>  				       unsigned long *prate)
>  {
> -	return clamp_val(rate, 125000000, 1600000000);
> +	return clamp_val(rate, 125000000, 2500000000);
>  }
>  
>  static const struct clk_ops mtk_mipi_tx_pll_ops = {
> -- 
> 2.45.2

-- 
~Vinod