linux-kernel - Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

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Message-ID: <20250820231917-GYB1065530@gentoo>
Date: Thu, 21 Aug 2025 07:19:17 +0800
From: Yixun Lan <dlan@...too.org>
To: Hendrik Hamerlinck <hendrik.hamerlinck@...mernet.be>
Cc: robh@...nel.org, krzk+dt@...nel.org, conor+dt@...nel.org,
	paul.walmsley@...ive.com, palmer@...belt.com, aou@...s.berkeley.edu,
	alex@...ti.fr, skhan@...uxfoundation.org,
	linux-kernel-mentees@...ts.linux.dev, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, spacemit@...ts.linux.dev,
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] riscv: dts: spacemit: add UART resets for Soc K1

Hi Hendrik, 

On 21:18 Thu 07 Aug     , Hendrik Hamerlinck wrote:
> Add reset control entries for all UARTs in the SpaceMIT K1 SoC Device Tree.
> UART0 was functional as it did not need a reset. But the other UARTs were
> unable to access their registers without the reset being applied.
> 
..
> Although perhaps not needed I did add the reset for UART0 as well,
> to ensure consistency across all UARTs. With the current-speed set to
> 112500 baud rate, it matches the factory U-Boot settings.
> This should not give issues with early console usage. But perhaps it could
> be a good idea to let somebody else confirm this as well.
> 
Adding reset to UART0 is just fine, so we don't need to presume it will
rely on bootloader to de-assert the controller

please write changelogs in imperative mood, you can follow
https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog

> Tested this locally on both Orange Pi RV2 and Banana Pi BPI-F3 boards. 
> I enabled the UART9 and was able to use it successfully.
> 
> Signed-off-by: Hendrik Hamerlinck <hendrik.hamerlinck@...mernet.be>
> ---
>  arch/riscv/boot/dts/spacemit/k1.dtsi | 10 ++++++++++
>  1 file changed, 10 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi
> index abde8bb07c95..7a5196a98085 100644
> --- a/arch/riscv/boot/dts/spacemit/k1.dtsi
> +++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
> @@ -667,6 +667,8 @@ uart0: serial@...17000 {
>  				clocks = <&syscon_apbc CLK_UART0>,
>  					 <&syscon_apbc CLK_UART0_BUS>;
>  				clock-names = "core", "bus";
..
> +				current-speed = <115200>;
please drop this property, dtsi file should contain generic info for SoC,
even in real cases, all boards use UART0 as serial output and configured
at baudrate 115200, it still be able to alter to different frequency..

besides, if you really want to set baudrate, then I'd suggest to configure
it at board specific dts file, 
  stdout-path = "serial0:115200n8";

> +				resets = <&syscon_apbc RESET_UART0>;
>  				interrupts = <42>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -680,6 +682,7 @@ uart2: serial@...17100 {
>  				clocks = <&syscon_apbc CLK_UART2>,
>  					 <&syscon_apbc CLK_UART2_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART2>;
>  				interrupts = <44>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -693,6 +696,7 @@ uart3: serial@...17200 {
>  				clocks = <&syscon_apbc CLK_UART3>,
>  					 <&syscon_apbc CLK_UART3_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART3>;
>  				interrupts = <45>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -706,6 +710,7 @@ uart4: serial@...17300 {
>  				clocks = <&syscon_apbc CLK_UART4>,
>  					 <&syscon_apbc CLK_UART4_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART4>;
>  				interrupts = <46>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -719,6 +724,7 @@ uart5: serial@...17400 {
>  				clocks = <&syscon_apbc CLK_UART5>,
>  					 <&syscon_apbc CLK_UART5_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART5>;
>  				interrupts = <47>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -732,6 +738,7 @@ uart6: serial@...17500 {
>  				clocks = <&syscon_apbc CLK_UART6>,
>  					 <&syscon_apbc CLK_UART6_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART6>;
>  				interrupts = <48>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -745,6 +752,7 @@ uart7: serial@...17600 {
>  				clocks = <&syscon_apbc CLK_UART7>,
>  					 <&syscon_apbc CLK_UART7_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART7>;
>  				interrupts = <49>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -758,6 +766,7 @@ uart8: serial@...17700 {
>  				clocks = <&syscon_apbc CLK_UART8>,
>  					 <&syscon_apbc CLK_UART8_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART8>;
>  				interrupts = <50>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> @@ -771,6 +780,7 @@ uart9: serial@...17800 {
>  				clocks = <&syscon_apbc CLK_UART9>,
>  					 <&syscon_apbc CLK_UART9_BUS>;
>  				clock-names = "core", "bus";
> +				resets = <&syscon_apbc RESET_UART9>;
>  				interrupts = <51>;
>  				reg-shift = <2>;
>  				reg-io-width = <4>;
> -- 
> 2.43.0
> 

-- 
Yixun Lan (dlan)