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Message-ID: <e7653089-5c57-ee61-ed01-0b3245e10d82@gentwo.org>
Date: Wed, 20 Aug 2025 16:26:45 -0700 (PDT)
From: "Christoph Lameter (Ampere)" <cl@...two.org>
To: Yunhui Cui <cuiyunhui@...edance.com>
cc: yury.norov@...il.com, linux@...musvillemoes.dk, paul.walmsley@...ive.com,
palmer@...belt.com, aou@...s.berkeley.edu, alex@...ti.fr,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org,
dennis@...nel.org, tj@...nel.org, linux-mm@...ck.org
Subject: Re: [PATCH 2/2] riscv: introduce percpu.h into include/asm
On Tue, 19 Aug 2025, Yunhui Cui wrote:
> +#define __PERCPU_AMO_OP_CASE(sfx, name, sz, amo_insn) \
> +static inline void \
> +__percpu_##name##_amo_case_##sz(void *ptr, unsigned long val) \
> +{ \
> + asm volatile ( \
> + "amo" #amo_insn #sfx " zero, %[val], %[ptr]" \
> + : [ptr] "+A" (*(u##sz *)ptr) \
> + : [val] "r" ((u##sz)(val)) \
> + : "memory"); \
> +}
AMO creates a single instruction that performs the operation?
> +#define _pcp_protect(op, pcp, ...) \
> +({ \
> + preempt_disable_notrace(); \
> + op(raw_cpu_ptr(&(pcp)), __VA_ARGS__); \
> + preempt_enable_notrace(); \
> +})
Is "op" a single instruction? If so then preempt disable / endable would
not be needed if there is no other instruction created.
But raw_cpu_ptr performs a SHIFT_PERCPU_PTR which performs an addition.
So you need the disabling of preemption to protect the add.
Is there a way on RISC V to embedd the pointer arithmetic in the "AMO"
instruction? Or can you use relative addressing to a register that
contains the cpu offset. I believe RISC V has a thread pointer?
If you can do this then a lot of preempt_enable/disable points can be
removed from the core kernel and the instruction may be as scalable as x86
which can do the per cpu operations with a single instruction.
> +
> +#define _pcp_protect_return(op, pcp, args...) \
> +({ \
> + typeof(pcp) __retval; \
> + preempt_disable_notrace(); \
> + __retval = (typeof(pcp))op(raw_cpu_ptr(&(pcp)), ##args); \
> + preempt_enable_notrace(); \
> + __retval; \
> +})
Same here.
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