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Message-ID: <3738425.aeNJFYEL58@senjougahara>
Date: Wed, 20 Aug 2025 13:35:08 +0900
From: Mikko Perttunen <mperttunen@...dia.com>
To: "Rafael J. Wysocki" <rafael@...nel.org>,
 Daniel Lezcano <daniel.lezcano@...aro.org>, Zhang Rui <rui.zhang@...el.com>,
 Lukasz Luba <lukasz.luba@....com>, Thierry Reding <thierry.reding@...il.com>,
 Thierry Reding <treding@...dia.com>, Jonathan Hunter <jonathanh@...dia.com>,
 Svyatoslav Ryhel <clamor95@...il.com>, Svyatoslav Ryhel <clamor95@...il.com>
Cc: linux-pm@...r.kernel.org, devicetree@...r.kernel.org,
 linux-tegra@...r.kernel.org, linux-kernel@...r.kernel.org
Subject:
 Re: [PATCH v2 3/5] thermal: tegra: soctherm-fuse: parametrize configuration
 further

On Monday, July 14, 2025 5:22 PM Svyatoslav Ryhel wrote:
> Prepare soctherm fuse calibration for Tegra114 support.

Please describe the changes that are needed for Tegra114 in the commit 
message.

> 
> Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com>
> ---
>  drivers/thermal/tegra/soctherm-fuse.c     | 33 ++++++++++++++++-------
>  drivers/thermal/tegra/soctherm.h          | 13 ++++++++-
>  drivers/thermal/tegra/tegra124-soctherm.c |  8 ++++++
>  drivers/thermal/tegra/tegra132-soctherm.c |  8 ++++++
>  drivers/thermal/tegra/tegra210-soctherm.c |  8 ++++++
>  5 files changed, 59 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/thermal/tegra/soctherm-fuse.c
> b/drivers/thermal/tegra/soctherm-fuse.c index 190f95280e0b..3b808c4521b8
> 100644
> --- a/drivers/thermal/tegra/soctherm-fuse.c
> +++ b/drivers/thermal/tegra/soctherm-fuse.c
> @@ -9,15 +9,10 @@
> 
>  #include "soctherm.h"
> 
> -#define NOMINAL_CALIB_FT			105
> -#define NOMINAL_CALIB_CP			25
> -
>  #define FUSE_TSENSOR_CALIB_CP_TS_BASE_MASK	0x1fff
>  #define FUSE_TSENSOR_CALIB_FT_TS_BASE_MASK	(0x1fff << 13)
>  #define FUSE_TSENSOR_CALIB_FT_TS_BASE_SHIFT	13
> 
> -#define FUSE_TSENSOR_COMMON			0x180
> -
>  /*
>   * Tegra210: Layout of bits in FUSE_TSENSOR_COMMON:
>   *    3                   2                   1                   0
> @@ -44,6 +39,13 @@
>   * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>   * |---------------------------------------------------| SHIFT_CP  |
>   * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + *
> + * Tegra11x: Layout of bits in FUSE_TSENSOR_COMMON aka FUSE_VSENSOR_CALIB:

Let's just call it Tegra114. I see 'Tegra12x' is used above. You can change 
that to 'Tegra124/Tegra132' while at it. The 'NNx' numbering is something 
leaking from (old) downstream code that we're trying to avoid.

> + *    3                   2                   1                   0
> + *  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
> + * | SHFT_FT |       BASE_FT       | SHIFT_CP  |      BASE_CP      |
> + * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
>   */

Based on these diagrams, the size of e.g. SHIFT_FT has not changed between the 
chip generations. I checked old downstream code, where

  #define FUSE_SHIFT_FT_BITS      5

Below, we have

  shifted_ft = sign_extend32(shifted_ft, 4);

However, sign_extend32 calculates as '31 - x' whereas the downstream code does 
'32 - x'. So it appears to me that the size hasn't changed between the chips 
and hence we don't need the added parameterization? Same might apply to other 
fields in the calibration data.

> 
>  #define CALIB_COEFFICIENT 1000000LL
> @@ -77,7 +79,7 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse, s32 shifted_cp, shifted_ft;
>  	int err;
> 
> -	err = tegra_fuse_readl(FUSE_TSENSOR_COMMON, &val);
> +	err = tegra_fuse_readl(tfuse->fuse_common_reg, &val);
>  	if (err)
>  		return err;
> 
> @@ -88,7 +90,7 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse,
> 
>  	shifted_ft = (val & tfuse->fuse_shift_ft_mask) >>
>  		     tfuse->fuse_shift_ft_shift;
> -	shifted_ft = sign_extend32(shifted_ft, 4);
> +	shifted_ft = sign_extend32(shifted_ft, tfuse->fuse_shift_ft_bits);
> 
>  	if (tfuse->fuse_spare_realignment) {
>  		err = tegra_fuse_readl(tfuse->fuse_spare_realignment, &val);
> @@ -96,10 +98,21 @@ int tegra_calc_shared_calib(const struct
> tegra_soctherm_fuse *tfuse, return err;
>  	}
> 
> -	shifted_cp = sign_extend32(val, 5);
> +	shifted_cp = (val & tfuse->fuse_shift_cp_mask) >>
> +		     tfuse->fuse_shift_cp_shift;
> +	shifted_cp = sign_extend32(val, tfuse->fuse_shift_cp_bits);
> 
> -	shared->actual_temp_cp = 2 * NOMINAL_CALIB_CP + shifted_cp;
> -	shared->actual_temp_ft = 2 * NOMINAL_CALIB_FT + shifted_ft;
> +	shared->actual_temp_cp = 2 * tfuse->nominal_calib_cp + shifted_cp;
> +	shared->actual_temp_ft = 2 * tfuse->nominal_calib_ft + shifted_ft;
> +
> +	/*
> +	 * Tegra114 provides fuse thermal corrections in 0.5C while expected
> +	 * precision should be 1C
> +	 */

If Tegra114 is lower precision, should this say it provides corrections in 1C 
while newer chips are 0.5C?

> +	if (tfuse->lower_precision) {
> +		shared->actual_temp_cp /= 2;
> +		shared->actual_temp_ft /= 2;
> +	}
> 
>  	return 0;
>  }
> diff --git a/drivers/thermal/tegra/soctherm.h
> b/drivers/thermal/tegra/soctherm.h index 70501e73d586..6c0e0cc594a5 100644
> --- a/drivers/thermal/tegra/soctherm.h
> +++ b/drivers/thermal/tegra/soctherm.h
> @@ -56,6 +56,13 @@
>  #define SENSOR_TEMP2_MEM_TEMP_MASK		(0xffff << 16)
>  #define SENSOR_TEMP2_PLLX_TEMP_MASK		0xffff
> 
> +#define NOMINAL_CALIB_FT			105
> +#define T114X_CALIB_FT				90
> +#define NOMINAL_CALIB_CP			25

I would either just hardcode these values in the chip-specific files, or

#define TEGRA114_NOMINAL_CALIB_FT ...
#define TEGRA124_NOMINAL_CALIB_FT ...
#define TEGRA114_NOMINAL_CALIB_CP ...

> +
> +#define FUSE_VSENSOR_CALIB			0x08c
> +#define FUSE_TSENSOR_COMMON			0x180
> +
>  /**
>   * struct tegra_tsensor_group - SOC_THERM sensor group data
>   * @name: short name of the temperature sensor group
> @@ -109,9 +116,13 @@ struct tsensor_group_thermtrips {
> 
>  struct tegra_soctherm_fuse {
>  	u32 fuse_base_cp_mask, fuse_base_cp_shift;
> +	u32 fuse_shift_cp_mask, fuse_shift_cp_shift;
>  	u32 fuse_base_ft_mask, fuse_base_ft_shift;
>  	u32 fuse_shift_ft_mask, fuse_shift_ft_shift;
> -	u32 fuse_spare_realignment;
> +	u32 fuse_shift_cp_bits, fuse_shift_ft_bits;
> +	u32 fuse_common_reg, fuse_spare_realignment;
> +	u32 nominal_calib_cp, nominal_calib_ft;
> +	bool lower_precision;
>  };
> 
>  struct tsensor_shared_calib {
> diff --git a/drivers/thermal/tegra/tegra124-soctherm.c
> b/drivers/thermal/tegra/tegra124-soctherm.c index
> 20ad27f4d1a1..dd4dd7e9014d 100644
> --- a/drivers/thermal/tegra/tegra124-soctherm.c
> +++ b/drivers/thermal/tegra/tegra124-soctherm.c
> @@ -200,11 +200,19 @@ static const struct tegra_tsensor tegra124_tsensors[]
> = { static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = {
> .fuse_base_cp_mask = 0x3ff,
>  	.fuse_base_cp_shift = 0,
> +	.fuse_shift_cp_mask = 0x1f,
> +	.fuse_shift_cp_shift = 0,
>  	.fuse_base_ft_mask = 0x7ff << 10,
>  	.fuse_base_ft_shift = 10,
>  	.fuse_shift_ft_mask = 0x1f << 21,
>  	.fuse_shift_ft_shift = 21,
> +	.fuse_shift_cp_bits = 5,
> +	.fuse_shift_ft_bits = 4,
> +	.fuse_common_reg = FUSE_TSENSOR_COMMON,
>  	.fuse_spare_realignment = 0x1fc,
> +	.nominal_calib_cp = NOMINAL_CALIB_CP,
> +	.nominal_calib_ft = NOMINAL_CALIB_FT,
> +	.lower_precision = false,
>  };
> 
>  const struct tegra_soctherm_soc tegra124_soctherm = {
> diff --git a/drivers/thermal/tegra/tegra132-soctherm.c
> b/drivers/thermal/tegra/tegra132-soctherm.c index
> b76308fdad9e..926836426688 100644
> --- a/drivers/thermal/tegra/tegra132-soctherm.c
> +++ b/drivers/thermal/tegra/tegra132-soctherm.c
> @@ -200,11 +200,19 @@ static struct tegra_tsensor tegra132_tsensors[] = {
>  static const struct tegra_soctherm_fuse tegra132_soctherm_fuse = {
>  	.fuse_base_cp_mask = 0x3ff,
>  	.fuse_base_cp_shift = 0,
> +	.fuse_shift_cp_mask = 0x1f,
> +	.fuse_shift_cp_shift = 0,
>  	.fuse_base_ft_mask = 0x7ff << 10,
>  	.fuse_base_ft_shift = 10,
>  	.fuse_shift_ft_mask = 0x1f << 21,
>  	.fuse_shift_ft_shift = 21,
> +	.fuse_shift_cp_bits = 5,
> +	.fuse_shift_ft_bits = 4,
> +	.fuse_common_reg = FUSE_TSENSOR_COMMON,
>  	.fuse_spare_realignment = 0x1fc,
> +	.nominal_calib_cp = NOMINAL_CALIB_CP,
> +	.nominal_calib_ft = NOMINAL_CALIB_FT,
> +	.lower_precision = false,
>  };
> 
>  const struct tegra_soctherm_soc tegra132_soctherm = {
> diff --git a/drivers/thermal/tegra/tegra210-soctherm.c
> b/drivers/thermal/tegra/tegra210-soctherm.c index
> d0ff793f18c5..2877a7b43f2a 100644
> --- a/drivers/thermal/tegra/tegra210-soctherm.c
> +++ b/drivers/thermal/tegra/tegra210-soctherm.c
> @@ -201,11 +201,19 @@ static const struct tegra_tsensor tegra210_tsensors[]
> = { static const struct tegra_soctherm_fuse tegra210_soctherm_fuse = {
> .fuse_base_cp_mask = 0x3ff << 11,
>  	.fuse_base_cp_shift = 11,
> +	.fuse_shift_cp_mask = 0x1f,
> +	.fuse_shift_cp_shift = 0,
>  	.fuse_base_ft_mask = 0x7ff << 21,
>  	.fuse_base_ft_shift = 21,
>  	.fuse_shift_ft_mask = 0x1f << 6,
>  	.fuse_shift_ft_shift = 6,
> +	.fuse_shift_cp_bits = 5,
> +	.fuse_shift_ft_bits = 4,
> +	.fuse_common_reg = FUSE_TSENSOR_COMMON,
>  	.fuse_spare_realignment = 0,
> +	.nominal_calib_cp = NOMINAL_CALIB_CP,
> +	.nominal_calib_ft = NOMINAL_CALIB_FT,
> +	.lower_precision = false,
>  };
> 
>  static struct tsensor_group_thermtrips tegra210_tsensor_thermtrips[] = {





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