linux-kernel - [PATCH v2 3/3] riscv: dts: thead: Scope the reset controller to VO for TH1520

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Message-ID: <20250820074245.16613-4-ziyao@disroot.org>
Date: Wed, 20 Aug 2025 07:42:45 +0000
From: Yao Zi <ziyao@...root.org>
To: Drew Fustini <fustini@...nel.org>,
	Guo Ren <guoren@...nel.org>,
	Fu Wei <wefu@...hat.com>,
	Philipp Zabel <p.zabel@...gutronix.de>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Conor Dooley <conor+dt@...nel.org>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Palmer Dabbelt <palmer@...belt.com>,
	Albert Ou <aou@...s.berkeley.edu>,
	Alexandre Ghiti <alex@...ti.fr>,
	Michal Wilczynski <m.wilczynski@...sung.com>
Cc: linux-riscv@...ts.infradead.org,
	devicetree@...r.kernel.org,
	linux-kernel@...r.kernel.org,
	Icenowy Zheng <uwu@...nowy.me>,
	Han Gao <rabenda.cn@...il.com>,
	Han Gao <gaohan@...as.ac.cn>,
	Yao Zi <ziyao@...root.org>
Subject: [PATCH v2 3/3] riscv: dts: thead: Scope the reset controller to VO for TH1520

The only reset-controller described in TH1520's SoC devicetree takes
control of reset signals in VO subsystem, while using a generic
"thead,th1520-reset" compatible that may imply control over the whole
SoC.

To avoid such confusion, let's replace the compatible with the new
introduced "thead,th1520-reset-vo" that explicitly describes the
controller's scope. The controller's label is updated as well.

Fixes: 1b136de08b5f ("riscv: dts: thead: Introduce reset controller node")
Reported-by: Icenowy Zheng <uwu@...nowy.me>
Co-developed-by: Michal Wilczynski <m.wilczynski@...sung.com>
Signed-off-by: Michal Wilczynski <m.wilczynski@...sung.com>
Signed-off-by: Yao Zi <ziyao@...root.org>
---
 arch/riscv/boot/dts/thead/th1520.dtsi | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 03f1d7319049..025402f6aa21 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -235,7 +235,7 @@ aon: aon {
 		compatible = "thead,th1520-aon";
 		mboxes = <&mbox_910t 1>;
 		mbox-names = "aon";
-		resets = <&rst TH1520_RESET_ID_GPU_CLKGEN>;
+		resets = <&rst_vo TH1520_RESET_ID_GPU_CLKGEN>;
 		reset-names = "gpu-clkgen";
 		#power-domain-cells = <1>;
 	};
@@ -502,8 +502,8 @@ clk: clock-controller@...f010000 {
 			#clock-cells = <1>;
 		};
 
-		rst: reset-controller@...f528000 {
-			compatible = "thead,th1520-reset";
+		rst_vo: reset-controller@...f528000 {
+			compatible = "thead,th1520-reset-vo";
 			reg = <0xff 0xef528000 0x0 0x4f>;
 			#reset-cells = <1>;
 		};
-- 
2.50.1