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Message-ID: <20250821-pencil-anguished-6b8467adbd38@spud>
Date: Thu, 21 Aug 2025 19:17:29 +0100
From: Conor Dooley <conor@...nel.org>
To: Hal Feng <hal.feng@...rfivetech.com>
Cc: Conor Dooley <conor+dt@...nel.org>,
	Emil Renner Berthing <emil.renner.berthing@...onical.com>,
	Heinrich Schuchardt <heinrich.schuchardt@...onical.com>,
	Rob Herring <robh@...nel.org>,
	Krzysztof Kozlowski <krzk+dt@...nel.org>,
	Palmer Dabbelt <palmer@...belt.com>,
	Paul Walmsley <paul.walmsley@...ive.com>,
	Albert Ou <aou@...s.berkeley.edu>, devicetree@...r.kernel.org,
	linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [RFC 1/3] dt-bindings: riscv: Add StarFive JH7110S SoC and
 VisionFive 2 Lite board

On Thu, Aug 21, 2025 at 06:09:28PM +0800, Hal Feng wrote:
> Add device tree bindings for the StarFive JH7110S SoC
> and the VisionFive 2 Lite board equipped with it.
> 
> JH7110S SoC is an industrial SoC which can run at -40~85 degrees centigrade
> and up to 1.25GHz. Its CPU cores and peripherals are mostly similar to
> those of the JH7110 SoC.

How "mostly" is mostly? Are there memory map or capability differences?

> 
> Signed-off-by: Hal Feng <hal.feng@...rfivetech.com>
> ---
>  Documentation/devicetree/bindings/riscv/starfive.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml
> index 7ef85174353d..a2952490709f 100644
> --- a/Documentation/devicetree/bindings/riscv/starfive.yaml
> +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml
> @@ -33,6 +33,11 @@ properties:
>                - starfive,visionfive-2-v1.3b
>            - const: starfive,jh7110
>  
> +      - items:
> +          - enum:
> +              - starfive,visionfive-2-lite
> +          - const: starfive,jh7110s
> +
>  additionalProperties: true
>  
>  ...
> -- 
> 2.43.2
> 

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