linux-kernel - Re: [PATCH] clk: meson-g12a: fix bit range for fixed sys and hifi pll

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Message-ID: <CAFBinCA2XZfiY2ESDSp2WyM9r-XB_LSj9s91woU9iWoQKrp6QA@mail.gmail.com>
Date: Thu, 21 Aug 2025 22:42:51 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Da Xue <da@...re.computer>
Cc: Neil Armstrong <neil.armstrong@...aro.org>, Jerome Brunet <jbrunet@...libre.com>, 
	Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, 
	Kevin Hilman <khilman@...libre.com>, linux-amlogic@...ts.infradead.org, 
	linux-clk@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, 
	linux-kernel@...r.kernel.org
Subject: Re: [PATCH] clk: meson-g12a: fix bit range for fixed sys and hifi pll

On Thu, Aug 14, 2025 at 10:09 PM Da Xue <da@...re.computer> wrote:
>
> The bit range 17:0 does not match the datasheet for A311D / S905D3.
> Change the bit range to 19:0 for FIX and HIFI PLLs to match datasheet.
I have:
-  S905X3_Public_Datasheet_Hardkernel.pdf
-  S922X_Datasheet_Wesion.pdf
-  A311D_Datasheet_01_Wesion.pdf
These state (for all three PLLs) that .frac is [18:0] (that's shift =
0 and width = 19).
I get where you're coming from with 19:0 - in the context of this
patch this can be misleading as it would mean that the fractional
divider is 20 bits wide.

> There's no frac for sys pll so add that as well.
I first read this as sys pll does not have a fractional divider.
What do you think about: "The frac field for sys pll is missing so add
that as well"

I guess at this point this should include:
Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller")
> Signed-off-by: Da Xue <da@...re.computer>

[...]
Have you compared /sys/kernel/debug/meson-clk-msr/measure_summary and
/sys/kernel/debug/clk/clk_summary before/after this patch?
I'll test this during the weekend and then give my Tested/Reviewed by


Best regards,
Martin