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Message-ID: <20250822133318.312232-4-krzysztof.kozlowski@linaro.org>
Date: Fri, 22 Aug 2025 15:33:20 +0200
From: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To: Rob Herring <robh@...nel.org>,
Krzysztof Kozlowski <krzk+dt@...nel.org>,
Conor Dooley <conor+dt@...nel.org>,
Kunihiko Hayashi <hayashi.kunihiko@...ionext.com>,
Masami Hiramatsu <mhiramat@...nel.org>,
devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
Subject: [PATCH 2/2] arm64: dts: socionext: uniphier-pxs3: Add default PCI interrup controller address cells
Add missing address-cells 0 to the PCI interrupt node to silence W=1
warning:
uniphier-pxs3.dtsi:915.4-918.29: Warning (interrupt_map): /soc@...cie@...00000:interrupt-map:
Missing property '#address-cells' in node /soc@...cie@...00000/legacy-interrupt-controller, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
---
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
index d6e3cc6fdb25..4d6c3c2dbea6 100644
--- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
+++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
@@ -921,6 +921,7 @@ pcie: pcie@...00000 {
pcie_intc: legacy-interrupt-controller {
interrupt-controller;
+ #address-cells = <0>;
#interrupt-cells = <1>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
--
2.48.1
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