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Message-ID: <20250822145934.GA3791610-robh@kernel.org> Date: Fri, 22 Aug 2025 09:59:34 -0500 From: Rob Herring <robh@...nel.org> To: Svyatoslav Ryhel <clamor95@...il.com> Cc: Krzysztof Kozlowski <krzk@...nel.org>, Conor Dooley <conor+dt@...nel.org>, Thierry Reding <treding@...dia.com>, Thierry Reding <thierry.reding@...il.com>, Jonathan Hunter <jonathanh@...dia.com>, Prashant Gaikwad <pgaikwad@...dia.com>, Mikko Perttunen <mperttunen@...dia.com>, Michael Turquette <mturquette@...libre.com>, Stephen Boyd <sboyd@...nel.org>, Jonathan Cameron <Jonathan.Cameron@...wei.com>, Dmitry Osipenko <digetx@...il.com>, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-tegra@...r.kernel.org, linux-clk@...r.kernel.org Subject: Re: [PATCH v2 2/9] dt-bindings: memory: Document Tegra114 Memory Controller On Wed, Aug 20, 2025 at 06:13:16PM +0300, Svyatoslav Ryhel wrote: > Add Tegra114 suffort into existing Tegra124 MC schema with the most notable > difference in the amount of EMEM timings. > > Signed-off-by: Svyatoslav Ryhel <clamor95@...il.com> > --- > .../nvidia,tegra124-mc.yaml | 106 +++++++++++++----- > 1 file changed, 80 insertions(+), 26 deletions(-) > > diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml > index 7b18b4d11e0a..e2568040213d 100644 > --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml > +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml > @@ -19,7 +19,9 @@ description: | > > properties: > compatible: > - const: nvidia,tegra124-mc > + enum: > + - nvidia,tegra114-mc > + - nvidia,tegra124-mc > > reg: > maxItems: 1 > @@ -62,31 +64,7 @@ patternProperties: > minimum: 1000000 > maximum: 1066000000 > > - nvidia,emem-configuration: > - $ref: /schemas/types.yaml#/definitions/uint32-array The type should stay here. It is not conditional. > - description: | > - Values to be written to the EMEM register block. See section > - "15.6.1 MC Registers" in the TRM. > - items: > - - description: MC_EMEM_ARB_CFG > - - description: MC_EMEM_ARB_OUTSTANDING_REQ > - - description: MC_EMEM_ARB_TIMING_RCD > - - description: MC_EMEM_ARB_TIMING_RP > - - description: MC_EMEM_ARB_TIMING_RC > - - description: MC_EMEM_ARB_TIMING_RAS > - - description: MC_EMEM_ARB_TIMING_FAW > - - description: MC_EMEM_ARB_TIMING_RRD > - - description: MC_EMEM_ARB_TIMING_RAP2PRE > - - description: MC_EMEM_ARB_TIMING_WAP2PRE > - - description: MC_EMEM_ARB_TIMING_R2R > - - description: MC_EMEM_ARB_TIMING_W2W > - - description: MC_EMEM_ARB_TIMING_R2W > - - description: MC_EMEM_ARB_TIMING_W2R > - - description: MC_EMEM_ARB_DA_TURNS > - - description: MC_EMEM_ARB_DA_COVERS > - - description: MC_EMEM_ARB_MISC0 > - - description: MC_EMEM_ARB_MISC1 > - - description: MC_EMEM_ARB_RING1_THROTTLE > + nvidia,emem-configuration: true > > required: > - clock-frequency > @@ -109,6 +87,82 @@ required: > - "#iommu-cells" > - "#interconnect-cells" > > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra114-mc > + then: > + patternProperties: > + "^emc-timings-[0-9]+$": > + patternProperties: > + "^timing-[0-9]+$": > + properties: > + nvidia,emem-configuration: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: | Drop '|'. > + Values to be written to the EMEM register block. See section > + "20.11.1 MC Registers" in the TRM. > + items: > + - description: MC_EMEM_ARB_CFG > + - description: MC_EMEM_ARB_OUTSTANDING_REQ > + - description: MC_EMEM_ARB_TIMING_RCD > + - description: MC_EMEM_ARB_TIMING_RP > + - description: MC_EMEM_ARB_TIMING_RC > + - description: MC_EMEM_ARB_TIMING_RAS > + - description: MC_EMEM_ARB_TIMING_FAW > + - description: MC_EMEM_ARB_TIMING_RRD > + - description: MC_EMEM_ARB_TIMING_RAP2PRE > + - description: MC_EMEM_ARB_TIMING_WAP2PRE > + - description: MC_EMEM_ARB_TIMING_R2R > + - description: MC_EMEM_ARB_TIMING_W2W > + - description: MC_EMEM_ARB_TIMING_R2W > + - description: MC_EMEM_ARB_TIMING_W2R > + - description: MC_EMEM_ARB_DA_TURNS > + - description: MC_EMEM_ARB_DA_COVERS > + - description: MC_EMEM_ARB_MISC0 > + - description: MC_EMEM_ARB_RING1_THROTTLE > + > + - if: > + properties: > + compatible: > + contains: > + enum: > + - nvidia,tegra124-mc > + then: > + patternProperties: > + "^emc-timings-[0-9]+$": > + patternProperties: > + "^timing-[0-9]+$": > + properties: > + nvidia,emem-configuration: > + $ref: /schemas/types.yaml#/definitions/uint32-array > + description: | > + Values to be written to the EMEM register block. See section > + "15.6.1 MC Registers" in the TRM. > + items: > + - description: MC_EMEM_ARB_CFG > + - description: MC_EMEM_ARB_OUTSTANDING_REQ > + - description: MC_EMEM_ARB_TIMING_RCD > + - description: MC_EMEM_ARB_TIMING_RP > + - description: MC_EMEM_ARB_TIMING_RC > + - description: MC_EMEM_ARB_TIMING_RAS > + - description: MC_EMEM_ARB_TIMING_FAW > + - description: MC_EMEM_ARB_TIMING_RRD > + - description: MC_EMEM_ARB_TIMING_RAP2PRE > + - description: MC_EMEM_ARB_TIMING_WAP2PRE > + - description: MC_EMEM_ARB_TIMING_R2R > + - description: MC_EMEM_ARB_TIMING_W2W > + - description: MC_EMEM_ARB_TIMING_R2W > + - description: MC_EMEM_ARB_TIMING_W2R > + - description: MC_EMEM_ARB_DA_TURNS > + - description: MC_EMEM_ARB_DA_COVERS > + - description: MC_EMEM_ARB_MISC0 > + - description: MC_EMEM_ARB_MISC1 > + - description: MC_EMEM_ARB_RING1_THROTTLE I imagine every SoC is going to be slightly different. I really don't care to know what are all the magic registers in the list, so I would just drop all this and just document the length. Just treat it as opaque data like calibration data we have in other bindings. Rob
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