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Message-Id: <20250822155908.625553-2-18255117159@163.com>
Date: Fri, 22 Aug 2025 23:59:02 +0800
From: Hans Zhang <18255117159@....com>
To: bhelgaas@...gle.com,
helgaas@...nel.org,
linux-pci@...r.kernel.org,
linux-kernel@...r.kernel.org
Cc: Hans Zhang <18255117159@....com>
Subject: [PATCH v2 1/7] PCI: Replace msleep(2) with fsleep() for precise delay
The msleep(2) may sleep longer than intended due to timer granularity.
According to PCIe r7.0 spec, section 7.5.1.3.13, the minimum Trst is 1ms.
We double this to 2ms to ensure we meet the requirement. Using fsleep()
provides a more precise delay.
Signed-off-by: Hans Zhang <18255117159@....com>
---
drivers/pci/pci.c | 7 ++-----
drivers/pci/pci.h | 6 ++++++
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b0f4d98036cd..fb4aff520f64 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4963,11 +4963,8 @@ void pci_reset_secondary_bus(struct pci_dev *dev)
ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
- /*
- * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
- * this to 2ms to ensure that we meet the minimum requirement.
- */
- msleep(2);
+ /* Wait for the reset to take effect */
+ fsleep(PCI_T_RST_SEC_BUS_DELAY_US);
ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 34f65d69662e..471dae45e46a 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -60,6 +60,12 @@ struct pcie_tlp_log;
#define PCIE_LINK_WAIT_MAX_RETRIES 10
#define PCIE_LINK_WAIT_SLEEP_MS 90
+/*
+ * PCIe r7.0, sec 7.5.1.3.13, requires minimum Trst of 1ms.
+ * Double this to 2ms to ensure we meet the minimum requirement.
+ */
+#define PCI_T_RST_SEC_BUS_DELAY_US 2000 /* 2ms */
+
/* Message Routing (r[2:0]); PCIe r6.0, sec 2.2.8 */
#define PCIE_MSG_TYPE_R_RC 0
#define PCIE_MSG_TYPE_R_ADDR 1
--
2.25.1
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