linux-kernel - RE: [PATCH v4 1/6] PCI: dwc: Remove the L1SS check before putting the link into L2

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Message-ID:
 <AS8PR04MB883352DA4438FE33A5996F6E8C3DA@AS8PR04MB8833.eurprd04.prod.outlook.com>
Date: Fri, 22 Aug 2025 09:07:09 +0000
From: Hongxing Zhu <hongxing.zhu@....com>
To: Frank Li <frank.li@....com>, "jingoohan1@...il.com"
	<jingoohan1@...il.com>, "l.stach@...gutronix.de" <l.stach@...gutronix.de>,
	"lpieralisi@...nel.org" <lpieralisi@...nel.org>, "kwilczynski@...nel.org"
	<kwilczynski@...nel.org>, "mani@...nel.org" <mani@...nel.org>,
	"robh@...nel.org" <robh@...nel.org>, "bhelgaas@...gle.com"
	<bhelgaas@...gle.com>, "shawnguo@...nel.org" <shawnguo@...nel.org>,
	"s.hauer@...gutronix.de" <s.hauer@...gutronix.de>, "kernel@...gutronix.de"
	<kernel@...gutronix.de>, "festevam@...il.com" <festevam@...il.com>
CC: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
	"linux-arm-kernel@...ts.infradead.org"
	<linux-arm-kernel@...ts.infradead.org>, "imx@...ts.linux.dev"
	<imx@...ts.linux.dev>, "linux-kernel@...r.kernel.org"
	<linux-kernel@...r.kernel.org>
Subject: RE: [PATCH v4 1/6] PCI: dwc: Remove the L1SS check before putting the
 link into L2

> -----Original Message-----
> From: Hongxing Zhu <hongxing.zhu@....com>
> Sent: 2025年8月22日 16:44
> To: Frank Li <frank.li@....com>; jingoohan1@...il.com;
> l.stach@...gutronix.de; lpieralisi@...nel.org; kwilczynski@...nel.org;
> mani@...nel.org; robh@...nel.org; bhelgaas@...gle.com;
> shawnguo@...nel.org; s.hauer@...gutronix.de; kernel@...gutronix.de;
> festevam@...il.com
> Cc: linux-pci@...r.kernel.org; linux-arm-kernel@...ts.infradead.org;
> imx@...ts.linux.dev; linux-kernel@...r.kernel.org; Hongxing Zhu
> <hongxing.zhu@....com>
> Subject: [PATCH v4 1/6] PCI: dwc: Remove the L1SS check before putting the
> link into L2
> 
> Since this L1SS check is just an encapsulation problem, and the ASPM
> shouldn't leak out here. Remove the L1SS check during L2 entry.
> 
> Fixes: 4774faf854f5 ("PCI: dwc: Implement generic suspend/resume
> functionality")
> Signed-off-by: Richard Zhu <hongxing.zhu@....com>
> ---
>  drivers/pci/controller/dwc/pcie-designware-host.c | 7 -------
>  1 file changed, 7 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
> b/drivers/pci/controller/dwc/pcie-designware-host.c
> index 952f8594b5012..1e130091d62a0 100644
> --- a/drivers/pci/controller/dwc/pcie-designware-host.c
> +++ b/drivers/pci/controller/dwc/pcie-designware-host.c
> @@ -1009,13 +1009,6 @@ int dw_pcie_suspend_noirq(struct dw_pcie *pci)
>  	u32 val;
>  	int ret;
> 
> -	/*
> -	 * If L1SS is supported, then do not put the link into L2 as some
> -	 * devices such as NVMe expect low resume latency.
> -	 */
> -	if (dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKCTL) &
> PCI_EXP_LNKCTL_ASPM_L1)
> -		return 0;
> -
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -1005,7 +1005,6 @@ static int dw_pcie_pme_turn_off(struct dw_pcie *pci)

 int dw_pcie_suspend_noirq(struct dw_pcie *pci)
 {
-       u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);

It's my fault that one line is missing to be deleted. This change would be
 added later with other review comments later.
Best Regards
Richard Zhu
>  	if (pci->pp.ops->pme_turn_off) {
>  		pci->pp.ops->pme_turn_off(&pci->pp);
>  	} else {
> --
> 2.37.1